METHODS FOR FABRICATING BULK FINFET DEVICES HAVING DEEP TRENCH ISOLATION
First Claim
1. A method for fabricating a bulk FinFET device having deep trench isolation comprising the steps of:
- forming one or more deep isolation trenches in a bulk silicon wafer;
depositing a mandrel-forming material on the bulk silicon wafer, the mandrel-forming material also substantially filling the one or more deep isolation trenches as filler material, wherein the mandrel-forming material comprises at least one of amorphous and polycrystalline silicon;
fabricating a plurality of mandrels from the mandrel-forming material and overetching the mandrel-forming material at an upper end of the one or more deep isolation trenches to form a recess;
depositing a sidewall spacer material overlying the plurality of mandrels and into the recess to form a spacer therein;
fabricating sidewall spacers from the sidewall spacer material, the sidewall spacers adjacent sidewalls of the plurality of mandrels;
removing the plurality of mandrels using the spacer as an etch stop;
etching the bulk silicon wafer to form a plurality of fin structures therefrom using the sidewall spacers as an etch mask.
4 Assignments
0 Petitions
Accused Products
Abstract
Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon.
44 Citations
20 Claims
-
1. A method for fabricating a bulk FinFET device having deep trench isolation comprising the steps of:
-
forming one or more deep isolation trenches in a bulk silicon wafer; depositing a mandrel-forming material on the bulk silicon wafer, the mandrel-forming material also substantially filling the one or more deep isolation trenches as filler material, wherein the mandrel-forming material comprises at least one of amorphous and polycrystalline silicon; fabricating a plurality of mandrels from the mandrel-forming material and overetching the mandrel-forming material at an upper end of the one or more deep isolation trenches to form a recess; depositing a sidewall spacer material overlying the plurality of mandrels and into the recess to form a spacer therein; fabricating sidewall spacers from the sidewall spacer material, the sidewall spacers adjacent sidewalls of the plurality of mandrels; removing the plurality of mandrels using the spacer as an etch stop; etching the bulk silicon wafer to form a plurality of fin structures therefrom using the sidewall spacers as an etch mask. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A method, comprising:
-
forming one or more deep isolation trenches in a bulk silicon wafer having a silicon oxide pad layer thereon; forming an insulating trench liner in the one or more deep isolation trenches; depositing a mandrel-forming material overlying the silicon oxide pad layer, the mandrel-forming material simultaneously substantially filling the one or more deep isolation trenches, wherein the mandrel-forming material comprises at least one of amorphous and polycrystalline silicon; fabricating a plurality of mandrels from the mandrel-forming material and overetching the mandrel-forming material at an upper end of the one or more deep isolation trenches to form a recess therein; depositing a conformal sidewall spacer material overlying the plurality of mandrels and filling the recess at the upper end of the one or more deep isolation trenches to form a spacer therein; fabricating sidewall spacers from the sidewall spacer material, the sidewall spacers adjacent sidewalls of the plurality of mandrels; removing the plurality of mandrels using the spacer as an etch stop; and etching the bulk silicon wafer to form a plurality of fin structures therefrom using the sidewall spacers as an etch mask. - View Dependent Claims (10, 11, 12, 13)
-
-
14. A method of forming inter-well isolation in a bulk FinFET device comprising the steps of:
-
forming one or more isolation trenches in a bulk silicon wafer having a dielectric pad layer, the one or more isolation trenches adapted to coincide with p- and n-well boundaries in the bulk silicon wafer; filling the one or more isolation trenches with at least one of amorphous and polycrystalline silicon to form filled isolation trenches; forming a plurality of fin structures from the bulk silicon wafer. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification