Layout Content Analysis for Source Mask Optimization Acceleration

• US 20110047519A1
• Filed: 05/11/2010
• Published: 02/24/2011
• Est. Priority Date: 05/11/2009
• Status: Abandoned Application

• Current Assignee: Juan Andres Torres Robles, Oberdan Otto, Yuri Granik
• Original Assignee: Juan Andres Torres Robles, Oberdan Otto, Yuri Granik
• Inventors: Granik, Yuri, Otto, Oberdan, Torres Robles, Juan Andres
• Application Number:
  US12/778,083
• Publication Number:
  US 20110047519A1
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G01R 31/26 Testing of individual semiconductor devices testing or measuring during manufacture or treatment H01L22/00; testing of photovoltaic devices H02S50/10
• CPC Class Codes: G03F 1/30 Alternating PSM, e.g. Levenson-Shibuya PSM; Preparation thereof
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/38 Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
• CPC Class Codes: G03F 1/68 Preparation processes not covered by groups G03F1/20 - G03F1/50
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: G21K 5/00 Irradiation devices discharge tubes for irradiating H01J37/00
• CPC Class Codes: H01L 21/00 Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign. In further implementations, the difficult-to-print sections may be subjected to a source mask optimization process. Subsequently, the entire layout design may receive a conventional resolution enhancement treatment using the optimized source.

Claims

1. A computer implemented method comprising:

identifying a layout design for a mask;

partitioning the layout design into a plurality of layout sections;

consolidating the plurality of layout sections into a plurality of pattern groups;

deriving a pattern group printing difficulty factor for ones of the plurality of pattern groups; and

marking ones of the plurality of layout sections for modification based in part upon the pattern group printing difficulty factor.

2. The computer implemented method recited in claim 1, further comprising saving the marked layout design to a memory storage location.

3. The computer implemented method recited in claim 2, the method act for partitioning the layout design into a plurality of layout sections comprising:

identifying a partition distance; and

splitting the layout design into layout sections of a similar geometric area, the geometric area being based in part upon the partition distance.

4. The computer implemented method recited in claim 3, the method act for consolidating the plurality of layout sections into a plurality of pattern groups comprising:

identifying a plurality of unique patterns based in part upon the geometric relationship of shapes defined by the plurality of layout sections;

forming a pattern group corresponding to each of the plurality of unique patterns;

for each of the pattern groups,

identifying ones of the plurality of layout sections where the geometric relationship of shapes defined by the identified ones of the plurality of layout sections are similar to the unique pattern associated with the pattern group, and

associating the identified ones of the plurality of layout sections with the pattern group.