Mechanism for Out-of-Synch Virtual Machine Memory Management Optimization

• US 20110047546A1
• Filed: 08/24/2009
• Published: 02/24/2011
• Est. Priority Date: 08/24/2009
• Status: Active Grant

• Current Assignee: Red Hat Israel Ltd. (International Business Machines Corporation)
• Original Assignee: Red Hat Israel Ltd. (International Business Machines Corporation)
• Inventors: Kivity, Avi, Tosatti, Marcelo
• Granted Patent: US 8,560,758 B2
• Time in Patent Office: Days
• US Class Current: 718/1
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

In one embodiment, a mechanism for out-of-synch virtual machine memory management optimization is disclosed. In one embodiment, a method for out-of-synch virtual machine memory management optimization includes receiving a memory management unit (MMU) synchronization event issued from a VM virtualized by a VM monitor (VMM) of a host server device, and synchronizing one or more unsynchronized page tables (PTs) of a shadow PT hierarchy maintained by the VMM with one or more corresponding guest PTs of a guest PT hierarchy maintained by the VM, wherein the one or more unsynchronized PTs include an unlimited number of unsynchronized PTs in a visible address space of the shadow PT hierarchy that is determined by a current CR3 register address of the shadow PT hierarchy.

Claims

1. A computer-implemented method, comprising:

receiving, by a virtual machine monitor (VMM) of a host virtual machine (VM) server device, a memory management unit (MMU) synchronization event issued from a VM virtualized by the VMM of the host server device; and

synchronizing, by the VMM, one or more unsynchronized page tables (PTs) of a shadow PT hierarchy maintained by the VMM with one or more corresponding guest PTs of a guest PT hierarchy maintained by the VM, wherein the one or more unsynchronized PTs include an unlimited number of unsynchronized PTs in a visible address space of the shadow PT hierarchy that is determined by a current CR3 register address of the shadow PT hierarchy.

2. The method of claim 1, wherein the MMU synchronization event includes at least one of a MOV to CR3 instruction, modification of CR0.PG, and toggling of a CR4.PGE bit.

3. The method of claim 1, wherein the CR3 register address is a base address of a highest-level PT associated with the shadow PT hierarchy.

4. The method of claim 1, wherein the shadow PT hierarchy includes a translation look-aside buffer (TLB) that emulates a functionality of a physical TLB of a processor of the host server device to the guest PT hierarchy of the VM.

5. The method of claim 1, wherein synchronizing the one or more unsynchronized PTs comprises:

traversing the shadow PT hierarchy by examining a bitmap associated with each PT of the shadow PT hierarchy, the bitmap including a flag for each entry of the corresponding PT that is set if there is an unsynchronized PT associated with that particular entry;

when an unsynchronized PT is reached via the traversing, propagating to the unsynchronized PT any changes found in a guest PT that corresponds to the unsynchronized PT; and

clearing one or more flags in any bitmap referring to the unsynchronized PT, as long as there are no other flags set in a PT referred to by the flag to be cleared.

6. The method of claim 5, further comprising repeating the traversing, propagating, and clearing until all flags in a bitmap of a highest-level PT associated with the current CR3 register address are cleared.

7. The method of claim 5, wherein the bitmap associated with each PT of the shadow PT hierarchy is a separate structure from the PT to which the bitmap refers.

8. The method of claim 1, wherein the VMM maintains a shadow PT hierarchy for each VM virtualized by the VMM.

9. A system, comprising:

a memory;

a processing device, communicably coupled to the memory;

one or more virtual machines (VMs) executed from the memory and sharing use of the processing device; and

a virtual machine manager (VMM) communicably coupled to the one or more VMs in order to manage the one or more VMs under a kernel-based virtualization model, the VMM operable to;

receive a memory management unit (MMU) synchronization event issued from a VM of the one or more VMs; and

synchronize one or more unsynchronized page tables (PTs) of a shadow PT hierarchy maintained by the VMM with one or more corresponding guest PTs of a guest PT hierarchy maintained by the VM, wherein the one or more unsynchronized PTs include an unlimited number of unsynchronized PTs in a visible address space of the shadow PT hierarchy that is determined by a current CR3 register address of the shadow PT hierarchy.

10. The system of claim 9, wherein the MMU synchronization event includes at least one of a MOV to CR3 instruction, modification of CR0.PG, and toggling of a CR4.PGE bit.

11. The system of claim 9, wherein the CR3 register address is a base address of a highest-level PT associated with the shadow PT hierarchy.

12. The system of claim 9, wherein the VMM to synchronize the one or more unsynchronized PTs further comprises the VMM to:

traverse the shadow PT hierarchy by examining a bitmap associated with each PT of the shadow PT hierarchy, the bitmap including a flag for each entry of the corresponding PT that is set if there is an unsynchronized PT associated with that particular entry;

when an unsynchronized PT is reached via the traversing, propagate to the unsynchronized PT any changes found in a guest PT that corresponds to the unsynchronized PT; and

clear one or more flags in any bitmap referring to the unsynchronized PT, as long as there are no other flags set in a PT referred to by the flag to be cleared.

13. The system of claim 12, wherein the VMM to synchronize the one or more unsynchronized PTs further comprises the VMM to repeat the traversing, propagating, and clearing until all flags in a bitmap of a highest-level PT associated with the current CR3 register address are cleared.

14. The system of claim 12, wherein the bitmap associated with each PT of the shadow PT hierarchy is a separate structure from the PT to which the bitmap refers.

15. The system of claim 9, wherein the VMM maintains a shadow PT hierarchy for each VM virtualized by the VMM.

16. An article of manufacture comprising a machine-readable storage medium including data that, when accessed by a machine, cause the machine to perform operations comprising:

receiving a memory management unit (MMU) synchronization event issued from a VM virtualized by a VM monitor (VMM) of a host server device; and

synchronizing one or more unsynchronized page tables (PTs) of a shadow PT hierarchy maintained by the VMM with one or more corresponding guest PTs of a guest PT hierarchy maintained by the VM, wherein the one or more unsynchronized PTs include an unlimited number of unsynchronized PTs in a visible address space of the shadow PT hierarchy that is determined by a current CR3 register address of the shadow PT hierarchy.

17. The article of manufacture of claim 16, wherein the MMU synchronization event includes at least one of a MOV to CR3 instruction, modification of CR0.PG, and toggling of a CR4.PGE bit.

18. The article of manufacture of claim 16, wherein the CR3 register address is a base address of a highest-level PT associated with the shadow PT hierarchy.

19. The article of manufacture of claim 16, wherein synchronizing the one or more unsynchronized PTs comprises:

traversing the shadow PT hierarchy by examining a bitmap associated with each PT of the shadow PT hierarchy, the bitmap including a flag for each entry of the corresponding PT that is set if there is an unsynchronized PT associated with that particular entry;

when an unsynchronized PT is reached via the traversing, propagating to the unsynchronized PT any changes found in a guest PT that corresponds to the unsynchronized PT;

clearing one or more flags in any bitmap referring to the unsynchronized PT, as long as there are no other flags set in a PT referred to by the flag to be cleared; and

repeating the traversing, propagating, and clearing until all flags in a bitmap of a highest-level PT associated with the current CR3 register address are cleared.

20. The article of manufacture of claim 19, wherein the bitmap associated with each PT of the shadow PT hierarchy is a separate structure from the PT to which the bitmap refers.