Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication

• US 20110049568A1
• Filed: 07/28/2010
• Published: 03/03/2011
• Est. Priority Date: 05/17/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Braithwaite, Glyn, Fiorenza, James, Lochtefeld, Anthony J., Currie, Matthew T., Langdo, Thomas A., Cheng, Zhiyuan
• Granted Patent: US 8,324,660 B2
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/02612 Formation types
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/778 : with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 : with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 31/028 : including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/0304 : including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 31/036 : characterised by their crystalline structure or particular orientation of the crystalline planes
• CPC Class Codes: H01L 31/1808 : including only Ge
• CPC Class Codes: H01L 33/20 : with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/30 : containing only elements of Group III and Group V of the Periodic Table
• CPC Class Codes: H01L 33/34 : containing only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/50 : Photovoltaic [PV] energy
• CPC Class Codes: Y02E 10/547 : Monocrystalline silicon PV cells

Abstract

Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Claims

1-40. -40. (canceled)

41. A semiconductor structure comprising:

(a) a substrate having a surface and comprising a first semiconductor material;

(b) a dislocation-blocking mask disposed over the substrate, the dislocation-blocking mask having a trench extending to the surface of the substrate, the trench being defined by at least one sidewall, the sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate, the trench exposing an exposed region of the substrate, the exposed region of the substrate having a substantially rectangular shape having a width w and a length l; and

(c) a regrowth layer comprising a second semiconductor material formed in the trench,

wherein a ratio of the height h to the width w is greater than 0.5, and wherein the length l is greater than the height h, and dislocation defects in the regrowth layer terminate at the sidewall of the trench at or below the predetermined distance H.

42. The structure of claim 41 wherein the first semiconductor material comprises silicon or a silicon germanium alloy.

43. The structure of claim 41, wherein the first semiconductor material consists essentially of silicon.

44. The structure of claim 41 wherein the second semiconductor material is selected from the group consisting of a group II, a group III, a group IV, a group V, and a group VI element, and a combination thereof.

45. The structure of claim 41, wherein the second semiconductor material is different from the first semiconductor material.

46. The structure of claim 41 wherein the surface of the substrate has a crystallographic orientation selected from the group consisting of:

(100), (110), and (111).

47. The structure of claim 41 wherein the dislocation-blocking mask comprises a dielectric material.

48. The structure of claim 47, wherein the dislocation-blocking mask consists essentially of at least one of silicon dioxide or silicon nitride.

49. The structure of claim 41, further comprising an overgrowth layer comprising the second semiconductor material disposed over the regrowth layer and over at least a portion of the dislocation-blocking mask.

50. The structure of claim 41, further comprising a layer of the second semiconductor material disposed over the substrate and below the mask.

51. The structure of claim 41, wherein the regrowth layer is disposed over and in direct contact with the surface of the substrate.

52. The structure of claim 41, wherein an orientation angle is defined in the surface of the substrate, the orientation angle being defined by a first line formed by where at least a portion of the sidewall meets the surface of the substrate and a second line formed by a direction of a selected crystallographic direction of the first semiconductor material, and the orientation angle causes the dislocation defects in the regrowth layer to decrease in density with increasing distance from the surface of the substrate.

53. The structure of claim 52 wherein the first semiconductor material is non-polar, the second semiconductor material is polar, and the orientation angle causes anti-phase boundaries in the regrowth layer to decrease in density with increasing distance from the surface of the substrate.

54. The structure of claim 52 wherein the crystallographic direction is aligned with at least one direction of propagation of the dislocation defects in the regrowth layer.

55. The structure of claim 41, wherein the length l is substantially non-parallel to a direction of propagation of threading dislocation defects in the regrowth layer.

56. The structure of claim 55, wherein the length l is generally perpendicular to the height h.

57. The structure of claim 41, wherein the length l is greater than the width w.

58. The structure of claim 57, wherein the length l is substantially in the same plane as the width w and generally perpendicular to the height h.

59. A structure comprising:

(a) a substrate having a surface and comprising a first semiconductor material;

(b) a dislocation-blocking mask disposed over the substrate, the mask having an opening extending to the surface of the substrate, the opening being defined by at least one sidewall, the sidewall having a first height h at least equal to a predetermined distance H from the surface of the substrate, the opening having a width W; and

(c) a regrowth layer comprising a second semiconductor material formed in the opening,

wherein the sidewall comprises a non-vertical slope, a cross-sectional area of the opening parallel to the surface of the substrate being substantially uniform across a second height of the non-vertical slope, and dislocation defects in the regrowth layer terminate at the sidewall of the opening at or below predetermined distance H.

60. The structure of claim 59, wherein a portion of the sidewall is substantially perpendicular to the surface of the substrate.

61. The structure of claim 59, wherein the regrowth layer is disposed over and in direct contact with the surface of the substrate.

62. A semiconductor structure comprising:

(a) a substrate having a surface and comprising a first semiconductor material,

(b) a dislocation-blocking mask disposed over the substrate, the mask having a trench extending to the surface of the substrate, the trench being defined by at least one sidewall, the sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate, the trench being substantially rectangular and having a width w;

(c) a regrowth layer comprising a second semiconductor material formed in the trench; and

(d) disposed directly below the trench, a recess in the substrate, wherein a portion of the regrowth layer is disposed in the recess,

wherein a ratio of the height h to the width w of the trench is greater than 0.5 and dislocation defects in the regrowth layer terminate at the sidewall of the trench at or below predetermined distance H.

63. The structure of claim 62, wherein a sidewall of the recess is substantially non-perpendicular to the surface of the substrate.

64. A semiconductor structure comprising:

(a) a substrate having a surface and comprising a first semiconductor material;

(b) a dislocation-blocking mask disposed over the substrate, the dislocation-blocking mask having a trench extending to the surface of the substrate, the trench being defined by at least one sidewall, the sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate, the trench exposing an exposed region of the substrate, the exposed region of the substrate having a substantially rectangular shape having a width w and a length l; and

(c) a regrowth layer comprising a second semiconductor material formed in the trench,

wherein the length l is greater than the height h, and dislocation defects in the regrowth layer terminate at the sidewall of the trench at or below the predetermined distance H.