Reverse Disturb Immune Asymmetrical Sidewall Floating Gate Devices and Methods

• US 20110049603A1
• Filed: 07/01/2010
• Published: 03/03/2011
• Est. Priority Date: 09/02/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shen, Ming-Hui, Pan, Jui-Yu, Hwang, Chung-Jen
• Granted Patent: US 8,334,560 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a semiconductor substrate comprising a floating gate, a charge trapping dielectric layer is formed, and a control gate is formed. The floating gate structure has vertical sidewalls, one side adjacent a source region and one side adjacent a drain region. A symmetric sidewall dielectric is formed over the floating gate structure on both the source side and drain side regions. An asymmetric dielectric layer is formed over the drain side sidewall only. The use of the asymmetric sidewall on the drain side sidewall provides improved RTD immunity. Methods for forming the structure are disclosed.

Claims

1. An apparatus, comprising:

a semiconductor substrate;

at least one floating gate structure having vertical sidewalls and comprising;

a floating gate disposed over the substrate;

a first dielectric layer disposed over the floating gate;

a control gate disposed over the first dielectric layer;

at least one dielectric disposed over the control gate;

a first symmetric vertical sidewall dielectric disposed over a source side sidewall and a drain side sidewall of the vertical sidewalls of the at least one floating gate structure; and

a second asymmetric vertical sidewall dielectric disposed over the first symmetric vertical sidewall dielectric over the drain side sidewalls of the floating gate structure.

2. The apparatus of claim 1, and further comprising a common source region formed in the substrate adjacent the source side sidewalls of the floating gate structure, the source region having a first side adjacent the source side sidewalls and a second opposing side.

3. The apparatus of claim 2 and further comprising:

a second floating gate structure disposed over the substrate adjacent the second side of the source region, the second floating gate structure further comprising;

a second floating gate disposed over the substrate;

a fourth dielectric layer disposed over the floating gate;

a control gate disposed over the fourth dielectric layer;

at least one dielectric disposed over the control gate;

a third symmetric vertical sidewall dielectric disposed over a source side sidewall and a drain side sidewall of the vertical sidewalls of the second floating gate structure; and

a fourth asymmetric vertical sidewall dielectric disposed over the third symmetric vertical sidewall dielectric only over the drain side sidewalls of the second floating gate structure.

4. The apparatus of claim 3, wherein the at least one floating gate structure and the second floating gate structure form floating gate cells that share a common source region.

5. The apparatus of claim 1 wherein the at least one floating gate structure forms a non-volatile memory cell.

6. The apparatus of claim 1 wherein the first symmetric vertical sidewall dielectric comprises a silicon nitride layer.

7. The apparatus of claim 1 wherein the second asymmetric vertical sidewall dielectric comprises a silicon nitride layer.

8. The apparatus of claim 1 and further comprising a tunnel oxide layer disposed over the first symmetric vertical sidewall dielectric.

9. The apparatus of claim 8 where the tunnel oxide layer comprise a high temperature oxide layer.

10. An integrated circuit device, comprising:

a semiconductor substrate;

at least one pair of floating gate cells formed adjacent a common source region in the substrate, each of the floating gate cells further comprising;

at least one floating gate structure having vertical sidewalls and comprising;

a floating gate disposed over the substrate;

a first dielectric layer disposed over the floating gate;

a control gate disposed over the first dielectric layer;

at least one dielectric disposed over the control gate;

a first symmetric vertical sidewall dielectric disposed over a source side sidewall and a drain side sidewall of the vertical sidewalls of the at least one floating gate structure; and

a second asymmetric vertical sidewall dielectric disposed over the first symmetric vertical sidewall dielectric over the drain side sidewalls of the floating gate structure.

11. The integrated circuit of claim 10 and further comprising a tunnel oxide layer disposed over the first symmetric vertical sidewall dielectric over the source side sidewalls of the floating gate structure.

12. The integrated circuit of claim 10 wherein the first symmetric vertical sidewall dielectric comprises a silicon nitride layer.

13. The integrated circuit of claim 12 wherein the second asymmetric vertical sidewall dielectric comprises a silicon nitride layer.

14. The integrated circuit of claim 13 wherein an etch stop layer is disposed between the first symmetric vertical sidewall dielectric and the second asymmetric vertical sidewall dielectric.

15. The integrated circuit of claim 10 and further comprising a common source region formed of dopant ions implanted into the substrate between the floating gate cells and adjacent the source side sidewalls.

16. A method, comprising:

providing a semiconductor substrate;

defining a source region on the semiconductor substrate;

forming at least one floating gate structure adjacent the source region and having vertical sidewalls, the vertical sidewall adjacent the source region forming a source side sidewall, the vertical sidewall away from the source region forming a drain side sidewall, the at least one floating gate structure comprising a floating gate, a dielectric layer over the floating gate, a control gate over the dielectric layer, and at least one dielectric layer over the control gate;

forming a first symmetric vertical sidewall dielectric over the floating gate structure and the substrate and on the source side and drain side sidewalls;

patterning a first photo resist over the first symmetric vertical sidewall dielectric;

removing the first symmetric vertical sidewall dielectric from the substrate while the first symmetric vertical sidewall dielectric remains on the source side and drain side sidewalls of the floating gate structure;

forming a second asymmetric vertical sidewall dielectric over the floating gate structure and the substrate;

patterning a second photo resist over the floating gate structure and the substrate; and

removing the second asymmetric vertical sidewall dielectric from the source side sidewall of the floating gate structure and the substrate while the second asymmetric vertical sidewall dielectric remains over the drain side sidewall.

17. The method of claim 16 wherein forming a first symmetric vertical sidewall dielectric comprises depositing silicon nitride.

18. The method of claim 16 wherein forming a second asymmetric vertical sidewall dielectric comprises depositing silicon nitride.

19. The method of claim 17 wherein forming a second asymmetric vertical sidewall dielectric comprises depositing an etch stop layer and depositing silicon nitride over the etch stop layer.

20. The method of claim 19 wherein removing the second asymmetric vertical sidewall dielectric from the source side sidewall of the floating gate structure and the substrate comprises performing a selective etch to remove the silicon nitride and stopping the selective etch on the etch stop layer.