SPLIT GATE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SPLIT GATE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE

• US 20110049605A1
• Filed: 08/02/2010
• Published: 03/03/2011
• Est. Priority Date: 08/28/2009
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: ISHIGURO, Hisashi
• Application Number:
  US12/848,488
• Publication Number:
  US 20110049605A1
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A split gate nonvolatile semiconductor storage device includes: a substrate; a floating gate; a control gate; a first source/drain diffusion layer; a second source/drain diffusion layer; and a silicide. The floating gate is formed on the substrate through a gate insulating film. The control gate is formed adjacent to the floating gate through a tunnel insulating film. The first source/drain diffusion layer is formed in a surface region of the substrate on a side of the floating gate. The second source/drain diffusion layer is formed in a surface region of the substrate on a side of the control gate. The silicide contacts the first source/drain diffusion layer.

Claims

1. A split gate nonvolatile semiconductor storage device comprising:

a substrate;

a floating gate configured to be formed on said substrate through a gate insulating film;

a control gate configured to be formed adjacent to said floating gate through a tunnel insulating film;

a first source/drain diffusion layer configured to be formed in a surface region of said substrate on a side of said floating gate;

a second source/drain diffusion layer configured to be formed in a surface region of said substrate on a side of said control gate; and

a silicide configured to contact said first source/drain diffusion layer.

2. The split gate nonvolatile semiconductor storage device according to claim 1, wherein said second source/drain diffusion layer is isolated by an insulating region from a second source/drain diffusion layer provided in an adjacent split gate nonvolatile semiconductor storage device, and

wherein said first source/drain diffusion layer is not isolated by said insulating region from a first source/drain diffusion layer provided in said adjacent split gate nonvolatile semiconductor storage device.

3. The split gate nonvolatile semiconductor storage device according to claim 1, further comprising:

a spacer insulating film configured to cover said floating gate; and

a side wall insulating film configured to cover a side wall of said floating gate,

wherein said floating gate includes;

an acute angle portion configured to be provided at an edge of a side of said control gate,

wherein said tunnel insulating film is provided between said floating gate and said control gate so as to cover said acute angle portion, and

wherein said side wall insulating film is provided on a side surface opposite to said acute angle portion of said floating gate.

4. The split gate nonvolatile semiconductor storage device according to claim 1, further comprising:

a first cell; and

a second cell,

wherein said first cell includes;

a first floating gate as said floating gate, and

a first control gate as said control gate,

said first source/drain diffusion layer, and

a third source/drain diffusion layer as said second source/drain diffusion layer,

wherein said second cell includes;

a second floating gate as said floating gate, and

a second control gates as said control gate,

said first source/drain diffusion layer, and

a fourth source/drain diffusion layer as said second source/drain diffusion layer,

wherein said first source/drain diffusion layer is shared by said first cell and said second cell, and

wherein said first cell and said second cell are symmetrical with respect to said first source/drain diffusion layer.

5. A split gate nonvolatile semiconductor storage device, comprising:

a first split gate nonvolatile memory cell; and

a second split gate nonvolatile memory cell,

wherein a source/drain diffusion layer is shared by said first split gate nonvolatile memory cell and said second split gate nonvolatile memory cell, and

wherein said first split gate nonvolatile memory cell and said second split gate nonvolatile memory cell are symmetrical with respect to said source/drain diffusion layer, and

wherein said source/drain diffusion layer directly contact a silicide.

6. A method of manufacturing a split gate nonvolatile semiconductor storage device, comprising:

forming a semiconductor structure, said semiconductor structure including;

a gate insulator formation film formed on a substrate,

a floating gate polysilicon film formed on said gate insulator formation film, and having a concave portion with a first slant portion at one end and a second slant portion at the other end,

a spacer formation insulating film formed on said floating gate polysilicon film, and having an opening portion with a first side surface extending upward from an end of said first slant portion and a second side surface extending upward from an end of said second slant portion, said opening port ion corresponding to said concave portion,

a first spacer insulating film covering said first slant portion and said first side surface, and

a second spacer insulating film covering said second slant portion and said second said surface;

removing said spacer formation insulating film without removing said first spacer insulating film and said second spacer insulating film to expose partially a surface of said floating gate polysilicon film;

removing selectively said floating gate polysilicon film and said gate insulator formation film using said first spacer insulating film and said second spacer insulating film as masks to form a floating gate with an acute portion and a gate insulating film while exposing partially said substrate;

forming a tunnel insulating film covering an exposed surface of said substrate, a side wall of said gate insulating film, and a side wall of said floating gate;

removing said tunnel insulating film between said first spacer insulating film and said second spacer insulating film to expose a surface of said substrate; and

forming a silicide between said first spacer insulating film and said second spacer insulating film.

7. The method of manufacturing a split gate nonvolatile semiconductor storage device according to claim 6, wherein said step of removing selectively said floating gate polysilicon film and said gate insulator formation film, includes:

removing said floating gate polysilicon film between said first spacer insulating film and said second spacer insulating film, and said floating gate polysilicon film outside said first spacer insulating film and said second spacer insulating film, at the same time.

8. The method of manufacturing a split gate nonvolatile semiconductor storage device according to claim 7, wherein said step of removing said tunnel insulating film, includes:

forming a control gate polysilicon film on said tunnel insulating film,

forming a control gate by etching back said control gate polysilicon film,

removing remains of said control gate polysilicon film, which remains between said first spacer insulating film and said second spacer insulating film after said control gate polysilicon film is etched back, to expose said tunnel insulating film, and

removing said exposed tunnel insulating film.

9. The method of manufacturing a split gate nonvolatile semiconductor storage device according to claim 8, wherein said step of removing said tunnel insulating film, further includes:

forming photoresist having an opening portion corresponding to a gap between said first spacer insulating film and said second spacer insulating film,

removing said control gate polysilicon film using said photoresist as a mask, and

removing said tunnel insulating film using said photoresist as a mask to expose a surface of said substrate.

10. The method of manufacturing a split gate nonvolatile semiconductor storage device according to claim 9, wherein said step of forming said silicide, includes:

forming a first side wall insulating film and a second side wall insulating film, said first side wall insulating film covering side walls of said gate insulating film and said floating gate on a side of said first spacer insulating film, and said second side wall insulating film covering side walls of said gate insulating film and said floating gate on a side of said second spacer insulating film, said first side wall insulating film and said second side wall insulating film being symmetrically arranged, and

forming said silicide between said first side wall insulating film and said second side wall insulating film.

11. The method of manufacturing a split gate nonvolatile semiconductor storage device according to claim 7, wherein said step of removing said tunnel insulating film, further includes:

forming photoresist having an opening portion corresponding to a gap between said first spacer insulating film and said second spacer insulating film,

removing said tunnel insulating film using said photoresist as a mask to expose a surface of said semiconductor substrate,

forming a control gate polysilicon film to cover surfaces of said tunnel insulating film and said semiconductor substrate, and

forming a control gate and a source plug by etching back said control gate polysilicon film.

12. The method of manufacturing a split gate nonvolatile semiconductor storage device according to claim 11, wherein said step of forming said silicide, includes:

forming said silicide on said source plug.

13. A method of manufacturing a split gate nonvolatile semiconductor storage device, comprising:

forming a first split gate nonvolatile memory cell and a second split gate nonvolatile memory cell, wherein a source/drain diffusion layer is shared by said first split gate nonvolatile memory cell and said second split gate nonvolatile memory cell, and wherein said first split gate nonvolatile memory cell and said second split gate nonvolatile memory cell are symmetrical with respect to said source/drain diffusion layer; and

forming a silicide so as to contact said source/drain diffusion layer.