SUPER JUNCTION TRENCH POWER MOSFET DEVICES

• US 20110049614A1
• Filed: 08/27/2009
• Published: 03/03/2011
• Est. Priority Date: 08/27/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Chau, The-Tu, Gao, Yang, Shi, Sharon, Pattanayak, Deva, Terrill, Kyle, Chen, Kuo-In, Chen, Qufei
• Granted Patent: US 9,425,306 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.

Claims

1. A super junction trench power metal oxide semiconductor field effect transistor (MOSFET) device having a channel of first type dopant, said device comprising:

a first column comprising insulating material that separates a column of second type dopant from a first column of said first type dopant;

a second column comprising insulating material that separates said column of said second type dopant from a second column of said first type dopant; and

a gate element for a field effect transistor, wherein said gate element is aligned between said first column of insulating material and said second column of insulating material.

2. The super junction trench power MOSFET device of claim 1 further comprising an isolation layer that separates said gate element from said column of said second type dopant.

3. The super junction trench power MOSFET device of claim 1 wherein if said first type dopant comprises n-type dopant then said second type dopant comprises p-type dopant, and wherein if said first type dopant comprises p-type dopant then said second type dopant comprises n-type dopant.

4. The super junction trench power MOSFET device of claim 1 further comprising a layer of source metal that is electrically shorted to said column of said second type dopant.

5. The super junction trench power MOSFET device of claim 4 further comprising a trench formed between said gate element and an adjacent gate element, wherein said source metal fills said trench.

6. The super junction trench power MOSFET device of claim 5 further comprising a body region of said second type dopant and a source region of said first type dopant disposed between said gate element and said trench.

7. The super junction trench power MOSFET device of claim 5 wherein said trench is aligned with the longitudinal axis of said first column of said first type dopant.

8. The super junction trench power MOSFET device of claim 7 wherein said trench is separated from said first column of said first type dopant by a region of said second type dopant.

9. A semiconductor device having a channel of first type dopant, said device comprising:

a substrate of said first type dopant;

a super junction structure coupled to said substrate and comprising a columnar region of second type dopant disposed between a columnar first region of said first type dopant and a columnar second region of said first type dopant, wherein said region of said second type dopant is separated from said first region of said first type dopant by a first isolation layer and from said second region of said first type dopant by a second isolation layer; and

a field effect transistor coupled to said super junction structure and comprising a gate element, wherein said gate element is aligned with the longitudinal axis of said region of said second type dopant.

10. The semiconductor device of claim 9 further comprising an oxide layer that separates said gate element from said region of said second type dopant.

11. The semiconductor device of claim 9 further comprising a layer of source metal that is electrically shorted to said region of said second type dopant.

12. The semiconductor device of claim 11 further comprising a trench formed between said gate element and an adjacent gate element, wherein said source metal fills said trench.

13. The semiconductor device of claim 12 further comprising a body region of said second type dopant and a source region of said first type dopant disposed between said gate element and said trench.

14. The semiconductor device of claim 12 wherein said trench is aligned with the longitudinal axis of said first region of said first type dopant.

15. A semiconductor device having a channel of first type dopant, comprising:

a substrate of said first type dopant;

a super junction structure coupled to said substrate and comprising a region of second type dopant disposed between a first region of said first type dopant and a second region of said first type dopant, wherein said region of said second type dopant and said first and second regions of said first type dopant each have a first dimension greater than a second dimension, said first dimension measured in a first direction and said second dimension measured in a second direction that is orthogonal to said first direction;

a field effect transistor comprising a gate element, wherein said region of said second type dopant lies between said gate element and said substrate in said first direction; and

a layer of source metal that is electrically shorted to said region of said second type dopant in a third direction that is orthogonal to both said first direction and said second direction.

16. The semiconductor device of claim 15 wherein said region of said second type dopant is separated from said first region of said first type dopant by a first isolation layer and from said second region of said first type dopant by a second isolation layer.

17. The semiconductor device of claim 15 further comprising an oxide layer that separates said gate element from said region of said second type dopant.

18. The semiconductor device of claim 15 further comprising a trench formed between said gate element and an adjacent gate element, wherein said source metal fills said trench.

19. The semiconductor device of claim 18 further comprising a body region of said second type dopant and a source region of said first type dopant disposed between said gate element and said trench.

20. The semiconductor device of claim 18 wherein said first region of said first type dopant lies between said trench and said substrate in said first direction.