Stressed Source/Drain CMOS and Method of Forming Same

• US 20110049630A1
• Filed: 08/31/2009
• Published: 03/03/2011
• Est. Priority Date: 08/31/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Wang, Xinhui, Majumdar, Amlan
• Granted Patent: US 9,059,318 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A complementary metal-oxide semiconductor (CMOS) structure includes a substrate and a P-type field effect transistor (FET) and an N-type FET disposed adjacent to one another on the substrate. Each FET includes a silicon-on-insulator (SOI) region, a gate electrode disposed on the SOI region, a source stressor, and a drain stressor disposed across from the source stressor relative to the gate electrode, wherein proximities of the source stressor and the drain stressor to a channel of a respective FET are substantially equal.

Claims

1. A complementary metal-oxide semiconductor (CMOS) structure comprising:

a substrate; and

a P-type field effect transistor (FET) and an N-type FET disposed adjacent to one another on the substrate, each FET comprising,

a silicon-on-insulator (SOI) region,

a gate electrode disposed on the SOI region,

a source stressor, and

a drain stressor disposed across from the source stressor relative to the gate electrode,

wherein proximities of the source stressor and the drain stressor to a channel of a respective FET are substantially equal.

2. The CMOS structure of claim 1, wherein the source stressor and the drain stressor are formed in the SOI region.

3. The CMOS structure of claim 1, wherein the source stressor and the drain stressor are formed on the SOI region.

4. The CMOS structure of claim 1, further comprising a shallow trench isolation region disposed between the respective SOI regions of the P-type FET and the N-type FET.

5. The CMOS structure of claim 1, wherein the channel is formed directly below the gate electrode.

6. The CMOS structure of claim 1, further comprising a spacer disposed between each the gate electrode and the SOI region.

7. A method for forming a complementary metal-oxide semiconductor (CMOS) structure with equal proximity of source/drain (SD) stressors to channels of adjacent N-type and P-type field effect transistors (FETs) formed on a substrate comprising:

forming a spacer comprising a stack comprising a top nitride layer, an oxide layer, and a lower nitride layer, wherein the lower nitride layer determines the proximity of the SD stressors to the channel for the N-type and P-type FETs;

forming a photoresist on the CMOS structure which covers the N-type FET and exposes the P-type FET;

implanting ions in an exposed portion of the top nitride layer of the P-type FET;

etching, selectively, an exposed portion of the top nitride layer and a portion of the oxide layer below the exposed portion of the top nitride layer;

removing the photoresist to expose the spacer on the N-type FET;

forming a nitride spacer on sidewalls of a gate electrode of the P-type FET, wherein remaining portions of the lower nitride layer on the P-type FET are removed;

forming the SD stressors of the P-type FET on opposite sides of the gate electrode, wherein a distance between the SD stressors and the P-type FET is controlled by the nitride spacer;

depositing a dielectric layer over the CMOS structure;

forming a photoresist on the CMOS structure which covers the P-type FET and exposes the N-type FET;

implanting ions in an exposed portion of the top nitride layer of the N-type FET;

etching, selectively, an exposed portion of the top nitride layer and a portion of the oxide layer below the exposed portion of the top nitride layer;

removing the photoresist to expose the spacer on the P-type FET;

forming a nitride spacer on sidewalls of a gate electrode of the N-type FET, wherein remaining portions of the lower nitride layer on the N-type FET are removed;

forming the SD stressors of the N-type FET on opposite sides of the gate electrode, wherein a distance between the SD stressors and the N-type FET is controlled by the nitride spacer; and

removing the dielectric layer from the P-type FET.

8. The method of claim 7, wherein the SD stressors are forming in a silicon-on-insulator formed between the gate electrode and the substrate.

9. The method of claim 7, wherein the SD stressors are forming on a silicon-on-insulator formed between the gate electrode and the substrate.

10. The structure of claim 7, wherein the nitride spacer of the P-type and N-type FETs have substantially the same width.

11. A method for forming a complementary metal-oxide semiconductor (CMOS) structure with equal proximity of source/drain (SD) stressors to channels of adjacent N-type and P-type field effect transistors (FETS) formed on a substrate comprising:

forming a spacer comprising a stack comprising a top nitride layer, an oxide layer, and a lower nitride layer, wherein the lower nitride layer determines the proximity of the SD stressors to the channel for the N-type and P-type FETs; and

forming, selectively, the SD stressors on opposite sides of gate electrodes of the N-type FET and the P-type FET, wherein the gate electrodes are formed on respective silicon-on-insulator layers.

12. The method of claim 11, wherein the SD stressors are forming in a silicon-on-insulator formed between the gate electrode and the substrate.

13. The method of claim 11, wherein the SD stressors are forming on a silicon-on-insulator formed between the gate electrode and the substrate.