SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20110049636A1
• Filed: 08/05/2010
• Published: 03/03/2011
• Est. Priority Date: 08/27/2009
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: OOIKE, Noboru
• Granted Patent: US 8,278,717 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

In one embodiment, a semiconductor memory device includes a semiconductor substrate, and isolation layers formed in a surface of the semiconductor substrate, and separating the semiconductor substrate into active areas, the isolation layers and the active areas being alternately arranged along a predetermined direction parallel to the surface of the semiconductor substrate, a height of upper surfaces of the isolation layers being lower than a height of an upper surface of the semiconductor substrate. The device further includes diffusion layers formed on surfaces of the active areas, and a stress liner formed on upper surfaces and side surfaces of the diffusion layers, and formed of a material having a lattice constant smaller than a lattice constant of a material formed of the semiconductor substrate.

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate;

isolation layers formed in a surface of the semiconductor substrate, and separating the semiconductor substrate into active areas, the isolation layers and the active areas being alternately arranged along a predetermined direction parallel to the surface of the semiconductor substrate, a height of upper surfaces of the isolation layers being lower than a height of an upper surface of the semiconductor substrate;

diffusion layers formed on surfaces of the active areas; and

a stress liner formed on upper surfaces and side surfaces of the diffusion layers, and formed of a material having a lattice constant smaller than a lattice constant of a material formed of the semiconductor substrate.

2. The device according to claim 1, wherein

the stress liner covers the side surfaces of the diffusion layers, located higher than bottom surfaces of the diffusion layers.

3. The device according to claim 1, wherein

the stress liner is continuously formed on the upper surfaces and side surfaces of the diffusion layers and on the upper surfaces of the isolation layers.

4. The device according to claim 1, wherein a thickness of the stress liner is 4 to 5 nm.

5. The device according to claim 1, wherein the stress liner has an amorphous structure or a diamond structure.

6. The device according to claim 1, wherein

the semiconductor substrate is a silicon substrate, and

the stress liner is an insulating layer containing silicon and nitrogen, or an insulating layer containing silicon and carbon.

7. The device according to claim 1, wherein

a height of bottom surfaces of the diffusion layers is lower than the height of the upper surfaces of the isolation layers.

8. A method of manufacturing a semiconductor memory device, the method comprising:

forming isolation layers on a surface of a semiconductor substrate to separate the substrate into active areas, the isolation layers and the active areas being arranged along a predetermined direction parallel to the surface of the semiconductor substrate;

forming diffusion layers on surfaces of the active areas;

forming a stress liner on upper surfaces of the diffusion layers, the stress liner being formed of a material having a lattice constant smaller than a lattice constant of a material formed of the semiconductor substrate; and

annealing the diffusion layers after the stress liner is formed.

9. The method according to claim 8, further comprising:

forming gate structures of cell transistors and of first and second select transistors arranged to sandwich the cell transistors, on the semiconductor substrate before the stress liner is formed; and

burying insulators between the cell transistors and between the cell transistors and the select transistors before the stress liner is formed, a compression stress of the insulators to the material formed of the substrate being smaller than a compression stress of the stress liner on the material formed of the substrate.

10. The method according to claim 9, further comprising:

removing the stress liner formed on the cell transistors and the select transistors, and on the insulators formed between the cell transistors and between the cell transistors and the select transistors.

11. The method according to claim 9, wherein the formation of the isolation layers to separate the substrate into the active areas comprises:

forming the isolation layers to make the height of the upper surfaces of the isolation layers be equal to or higher than the height of the upper surface of the semiconductor substrate, and then etching upper portions of the isolation layers to expose side surfaces of the diffusion layers

wherein the stress liner is formed on the side surfaces of the diffusion layers.

12. The method according to claim 11, wherein

the insulators buried between the cell transistors and between the cell transistors and the select transistors are also formed on the diffusion layers when the insulators are formed, and

the insulators formed on the diffusion layers are removed simultaneously with the etching of the upper portions of the isolation layers.

13. The method according to claim 11, wherein

the stress liner is continuously formed on the upper surfaces and side surfaces of the diffusion layers and on the upper surfaces of the isolation layers.

14. A semiconductor memory device comprising:

a semiconductor substrate;

isolation layers formed in a surface of the semiconductor substrate, and separating the semiconductor substrate into active areas, the isolation layers and the active areas being alternately arranged along a first direction parallel to the surface of the semiconductor substrate, and extending in a second direction perpendicular to the first direction, a height of upper surfaces of the isolation layers being lower than a height of an upper surface of the semiconductor substrate;

memory strings, each of the memory strings comprising;

cell transistors formed on one of the active areas along to the second direction, and

first and second select transistors formed on the active area and arranged to sandwich the cell transistors;

diffusion layers formed in surfaces of the active areas between the memory strings;

a stress liner formed on upper surfaces and side surfaces of the diffusion layers, and formed of a material having a lattice constant smaller than a lattice constant of a material formed of the semiconductor substrate; and

insulators buried between the cell transistors and between the cell transistors and the select transistors, a compression stress of the insulators to the material formed of the substrate being smaller than a compression stress of the stress liner to the material formed of the substrate.

15. The device according to claim 14, wherein

the memory strings are adjacent to each other in the second direction,

between the memory strings, the stress liner is formed on the side surfaces of the select transistors in the second direction, and on the upper surfaces and side surfaces of the diffusion layers in a section parallel to the first direction, and

in the memory strings, the stress liner is not formed between the cell transistors and between the cell transistors and the select transistors.

16. The device according to claim 14, wherein

a height of bottom surfaces of the diffusion layers is lower than the height of the upper surfaces of the isolation layers.

17. The device according to claim 14, further comprising:

peripheral transistors formed on the semiconductor substrate around a region where the cell transistors and the select transistors are formed,

each of the peripheral transistors comprising;

a gate insulator formed on the semiconductor substrate;

a gate electrode formed on the gate insulator; and

source and drain diffusion layers formed on the surface of the semiconductor substrate to sandwich the gate electrode,

wherein the stress liner is formed on side surfaces of the gate electrode.

18. The device according to claim 14, wherein

the stress liner covers the side surfaces of the diffusion layers, located higher than bottom surfaces of the diffusion layers.