ENCAPSULANT INTERPOSER SYSTEM WITH INTEGRATED PASSIVE DEVICES AND MANUFACTURING METHOD THEREFOR

• US 20110049687A1
• Filed: 11/09/2010
• Published: 03/03/2011
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Heap Hoe Kuan, Rui Huang, Seng Guan Chow, Yaojian Lin
• Inventors: Kuan, Heap Hoe, Chow, Seng Guan, Huang, Rui, Lin, Yaojian
• Granted Patent: US 8,258,612 B2
• Time in Patent Office: Days
• US Class Current: 257/667
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06579 : TAB carriers; beam leads
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/495 : Lead-frames or other flat leads H01L23/498 takes precedence; lead frame interconnections between components H01L23/52
• CPC Class Codes: H01L 23/49506 : an insulative substrate being used as a diepad, e.g. ceramic, plastic H01L23/49531 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49861 : Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A method of manufacturing a semiconductor package system includes: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.

Claims

1. A method of manufacturing for a semiconductor package system comprising:

forming a leadframe having a passive device;

encapsulating the passive device to form an encapsulant interposer;

attaching a first die to the encapsulant interposer;

forming a substrate interposer having a second die; and

stacking the encapsulant interposer over the substrate interposer.

2. The method as claimed in claim 1 wherein:

forming the leadframe includes forming a contact pad and a second dam bar;

encapsulating the passive device includes encapsulating the contact pad; and

further comprising;

singulating the leadframe to eliminate the second dam bar.

3. The method as claimed in claim 1 wherein:

forming the leadframe includes forming an external contact terminal connected to the passive device, and

further comprising;

bending the external contact terminal to a predetermined shape.

4. The method as claimed in claim 1 wherein forming a leadframe includes forming a leadframe having one or more than one row of the contact pad.

5. The method as claimed in claim 1 wherein forming the leadframe includes forming a leadframe having one or more inductors as the passive device.

6. A method of manufacturing for a semiconductor package system comprising:

forming a leadframe having a passive device;

encapsulating the passive device to form an encapsulant interposer,

attaching a first die to the encapsulant interposer;

forming a substrate interposer having a second die;

stacking the encapsulant interposer over the substrate interposer; and

encapsulating the encapsulant interposer, the first die, and the second die in a package mold compound.

7. The method as claimed in claim 6 wherein forming the leadframe includes forming a first inductor and a second inductor side by side.

8. The method as claimed in claim 6 wherein forming the leadframe includes forming a first inductor and a second inductor in unsymmetrical positions.

9. The method as claimed in claim 6 wherein forming the leadframe includes forming a jumper wire connecting a first inductor to a second inductor.

10. The method as claimed in claim 6 wherein forming the leadframe includes forming a selected number of the external contact terminal bent to a predetermined shape.

11. A semiconductor package system comprising:

an encapsulant interposer having a passive device encapsulated;

a first die connected to the encapsulant interposer; and

a substrate interposer having a second die, the encapsulant interposer being stacked over the substrate interposer.

12. The system as claimed in claim 11 wherein the encapsulant interposer having a passive device encapsulated has only one of the top or the bottom surface of the passive device exposed.

13. The system as claimed in claim 11 wherein the encapsulant interposer having a passive device encapsulated has neither of the top or the bottom surface of the passive device exposed.

14. The system as claimed in claim 11 wherein the encapsulant interposer having a passive device encapsulated has a connect bar bent to a predetermined shape.

15. The system as claimed in claim 11 further comprising:

a package mold compound encapsulating the encapsulant interposer, the first die, and the second die.

16. The system as claimed in claim 15 wherein the first die is electrically connected to the substrate interposer through a bonding wire.

17. The system as claimed in claim 15 wherein the package mold compound has a package mold compound opening, exposing the top surface of the encapsulant interposer.

18. The system as claimed in claim 15 wherein the first die is a first type flip chip die.

19. The system as claimed in claim 15 wherein the first die is a second type flip chip die.