SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND LEAD FRAME THEREOF

• US 20110049693A1
• Filed: 09/02/2010
• Published: 03/03/2011
• Est. Priority Date: 09/02/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: NAKASHIBA, Yasutaka, OGAWA, Kenta
• Granted Patent: US 8,378,470 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/29 of an individual layer connector
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29199 Material of the matrix
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29298 Fillers
• CPC Class Codes: H01L 2224/29299 Base material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83855 : Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/92147 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49534 : Multi-layer
• CPC Class Codes: H01L 23/49537 : Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01026 : Iron [Fe]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0635 : Acrylic polymer
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Claims

1. A semiconductor device comprising:

a first semiconductor chip that includes a first multilayer interconnect layer and a first inductor formed in said first multilayer interconnect layer; and

a second semiconductor chip that includes a second multilayer interconnect layer and a second inductor formed in said second multilayer interconnect layer,

wherein said first semiconductor chip and said second semiconductor chip are overlapped with each other in a direction in which said first multilayer interconnect layer and said second multilayer interconnect layer are opposed to each other,

said first inductor and said second inductor are overlapped when seen in a plan view,

said first semiconductor chip and said second semiconductor chip include non-opposed areas which are not opposed to each other,

said first multilayer interconnect layer includes a first external connection terminal in said non-opposed area, and

said second multilayer interconnect layer includes a second external connection terminal in said non-opposed area.

2. The semiconductor device according to claim 1,

wherein said first multilayer interconnect layer does not include an interconnect other than an interconnect connected to said first inductor in an area overlapped with said second semiconductor chip when seen in a plan view.

3. The semiconductor device according to claim 2,

wherein said second multilayer interconnect layer does not include an interconnect other than an interconnect connected to said second inductor in an area overlapped with said first semiconductor chip when seen in a plan view.

4. The semiconductor device according to claim 1, further comprising:

an insulating adhesive layer that fixes said first semiconductor chip and said second semiconductor chip to each other.

5. The semiconductor device according to claim 4,

wherein said adhesive layer is an insulating adhesive sheet.

6. The semiconductor device according to claim 1, further comprising:

a first lead frame in which said first semiconductor chip is mounted; and

a second lead frame in which said second semiconductor chip is mounted,

wherein said first lead frame and said second lead frame extend in directions different from each other.

7. The semiconductor device according to claim 6, further comprising:

a first bonding wire that connects said first lead frame to said first external connection terminal; and

a second bonding wire that connects said second lead frame to said second external connection terminal.

8. The semiconductor device according to claim 1, further comprising:

a lead frame that includes a die pad, a first lead, and a second lead,

wherein said first semiconductor chip is mounted over said die pad, and

said first lead is connected to said first semiconductor chip through a first bonding wire, and said second lead is connected to said second semiconductor chip through a second bonding wire.

9. The semiconductor device according to claim 8, further comprising:

a protective layer that is provided over the substrate side of said second semiconductor chip and covers said second semiconductor chip when seen in a plan view.

10. The semiconductor device according to claim 1,

wherein said first semiconductor chip includes a first polyimide layer provided over said first multilayer interconnect layer, and

said second semiconductor chip includes a second polyimide layer provided over said second multilayer interconnect layer.

11. The semiconductor device according to claim 10,

wherein said first semiconductor chip includes a first protective insulating film between said first multilayer interconnect layer and said first polyimide layer, and

said second semiconductor chip includes a second protective insulating film between said second multilayer interconnect layer and said second polyimide layer.

12. The semiconductor device according to claim 10,

wherein said first polyimide layer is not formed in an area located over said first inductor, and

said second polyimide layer is not formed in an area located over said second inductor.

13. The semiconductor device according to claim 1,

wherein said first semiconductor chip includes said first external connection terminal in the vicinity of a first side, and

said second semiconductor chip includes said second external connection terminal in the vicinity of a second side located on the side opposite to said first side when seen in a plan view.

14. The semiconductor device according to claim 1,

wherein when a diameter of said first inductor and said second inductor is D and a distance from said first inductor to said second inductor is x, x≦

D is satisfied.

15. A method of manufacturing a semiconductor device comprising:

face-up mounting a first semiconductor chip including a first multilayer interconnect layer, a first inductor formed in said first multilayer interconnect layer, and a first external connection terminal formed in said first multilayer interconnect layer, over a die pad of a first lead frame; and

overlapping a second semiconductor chip including a second multilayer interconnect layer, a second inductor formed in said second multilayer interconnect layer, and a second external connection terminal formed in said second multilayer interconnect layer, over said first semiconductor chip in a direction in which said first multilayer interconnect layer and said second multilayer interconnect layer are opposed to each other,

wherein in said step of overlapping of said first semiconductor chip and said second semiconductor chip with each other, said first semiconductor chip and said second semiconductor chip are provided with areas which are not opposed to each other, and said first external connection terminal and said second external connection terminal are located in the areas.

16. The method of manufacturing the semiconductor device according to claim 15, further comprising:

face-up mounting said second semiconductor chip over a die pad of the second lead frame before said step of overlapping of said second semiconductor chip over said first semiconductor chip.

17. The method of manufacturing the semiconductor device according to claim 15, further comprising:

providing said second semiconductor chip with a die pad of the second lead frame after said step of overlapping of said second semiconductor chip over said first semiconductor chip.

18. The method of manufacturing the semiconductor device according to claim 15,

wherein said first lead frame is provided with a first lead and a second lead, and

the method further comprising connecting said first lead to said first semiconductor chip by a first bonding wire, and connecting said second lead to said second semiconductor chip by a second bonding wire, after said step of overlapping of said second semiconductor chip over said first semiconductor chip.

19. The method of manufacturing the semiconductor device according to claim 15, further comprising:

providing said second semiconductor chip or said first semiconductor chip with an insulating adhesive sheet before said step of overlapping of said second semiconductor chip over said first semiconductor chip,

wherein in said step of overlapping of said second semiconductor chip over said first semiconductor chip, said first semiconductor chip and said second semiconductor chip are fixed to each other using said insulating adhesive sheet.

20. A lead frame comprising:

a die pad;

a first lead that extends outward from the vicinity of one side of said die pad; and

a second lead that extends outward from the vicinity of the other side different from said one side of said die pad,

wherein a distance from a leading end of said first lead to said die pad is different from a distance from a leading end of said second lead to said die pad.