OFF-CHIP VIAS IN STACKED CHIPS

• US 20110049696A1
• Filed: 11/08/2010
• Published: 03/03/2011
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Mohammed, Ilyas, Haba, Belgacem, Mirkarimi, Laura Wills, Ovrutsky, David, Oganesian, Vage
• Granted Patent: US 8,076,788 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Claims

1. A microelectronic assembly, comprising:

a first microelectronic element and a second microelectronic element, each of the first and second microelectronic elements having a front face, a rear face remote from the front face, a first edge extending between the front and rear faces, a second edge extending between the front and rear faces and being remote from the first edge, and a plurality of spaced apart traces extending along the front face and beyond at least the first edge, wherein a front face of the second microelectronic element overlies one of the front or rear faces of the first microelectronic element;

an insulating region contacting the first and second edges of the first and second microelectronic elements and at least portions of the traces of the first and second microelectronic elements extending beyond the respective first edges, the insulating region defining first and second side surfaces adjacent the first and second edges of each of the first and second microelectronic elements, the microelectronic assembly further including a plurality of spaced apart openings extending along a side surface selected from the first and second side surfaces; and

a plurality of electrical conductors each having at least a portion disposed in a respective opening of the plurality of openings and extending along the respective openings, the electrical conductors being electrically connected with respective ones of the traces of at least one of the first and second microelectronic elements.

2. A microelectronic assembly as claimed in claim 1, further comprising a substrate, wherein the front face of at least one of the first and second microelectronic elements faces toward the substrate.

3. A microelectronic assembly as claimed in claim 1, further comprising at least one of pads or solder bumps overlying the rear face of at least one of the first or second microelectronic elements, wherein the plurality of electrical conductors have portions contacting the at least one of pads or solder bumps.

4. A microelectronic assembly as claimed in claim 1, further comprising a protective layer overlying the rear face of at least one of the first and second microelectronic elements and at least one of pads or solder bumps overlying the protective layer, wherein the plurality of electrical conductors have portions contacting the at least one of pads or solder bumps.

5. The microelectronic assembly as claimed in claim 1, wherein the first and second edges of the second microelectronic element are at least substantially aligned with the first and second edges of the first microelectronic element.

6. The microelectronic assembly as claimed in claim 1, wherein the first edge of the second microelectronic element is offset in a lateral direction along the front face of the first microelectronic element from the first edge of the first microelectronic element.

7. The microelectronic assembly as claimed in claim 1, wherein each of the first and second microelectronic elements comprises a flash memory.

8. The microelectronic assembly as claimed in claim 1, wherein the electrical conductors extend onto a major surface of the microelectronic assembly.

9. The microelectronic assembly as claimed in claim 1, wherein each of the first and second microelectronic elements includes a flash memory.

10. The microelectronic assembly as claimed in claim 1, wherein the electrical conductors are exposed at the selected side surface of the microelectronic assembly.

11. The microelectronic assembly as claimed in claim 1, wherein the insulating region includes a first insulating region contacting the first and second edges of the first microelectronic element and a second insulating region contacting the first and second edges of the second microelectronic element, said first and second insulating regions attached together in said assembly.

12. The microelectronic assembly as claimed in claim 11, further comprising an adhesive layer attaching at least the first and second insulating regions.

13. The microelectronic assembly as claimed in claim 1, wherein at least some of the electrical conductors extend to selected different depths to contact selected ones of the traces.

14. A microelectronic device having at least two side external surfaces, said microelectronic device comprising:

a first substrate;

a first microelectronic element comprising a front face bonded to said first substrate and an opposing rear face;

said first microelectronic element further comprising a plurality of first traces extending along said front face, at least a portion of each said first trace extending beyond a first edge of said first microelectronic element, said first microelectronic element further comprising a second edge opposite said first edge;

a first insulating region disposed around said first and second edges of said first microelectronic element;

a second microelectronic element comprising a front face facing said opposing rear face of said first microelectronic element, said second microelectronic element further comprising a plurality of second traces extending along said front face of said second microelectronic element, at least a portion of each said second trace extending beyond a first edge of said second microelectronic element, said second microelectronic element further comprising a second edge opposite said first edge of said second microelectronic element,

a second insulating region disposed around said first and second edges of said second microelectronic element; and

at least one electrical conductor disposed on at least one of said side external surfaces of said microelectronic device, said electrical conductor being in electric contact with a cross-sectional edge of at least one of said plurality of said first and second traces.

15. The microelectronic device of claim 14 wherein said first and second edges of second microelectronic element are substantially aligned with said first and second edges of said first microelectronic element.

16. The microelectronic device of claim 14 wherein said first edge of said second microelectronic element is laterally offset from said first edge of said first microelectronic element.

17. The microelectronic device of claim 14 wherein each of said first and second microelectronic elements comprises a flash memory.