STRUCTURES OF AND METHODS AND TOOLS FOR FORMING IN-SITU METALLIC/DIELECTRIC CAPS FOR INTERCONNECTS

• US 20110049716A1
• Filed: 09/03/2009
• Published: 03/03/2011
• Est. Priority Date: 09/03/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Hu, Chao-Kun, Yang, Chih-Chao
• Granted Patent: US 8,039,966 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: C23C 16/0272 Deposition of sub-layers, e.g. to promote the adhesion of the main coating
• CPC Class Codes: C23C 16/16 from metal carbonyl compounds
• CPC Class Codes: C23C 16/325 Silicon carbide
• CPC Class Codes: C23C 16/345 Silicon nitride
• CPC Class Codes: C23C 16/36 Carbonitrides
• CPC Class Codes: C23C 16/54 Apparatus specially adapted for continuous coating
• CPC Class Codes: C23C 28/00 Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

A structure, tool and method for forming in-situ metallic/dielectric caps for interconnects. The method includes forming wire embedded in a dielectric layer on a semiconductor substrate, the wire comprising a copper core and an electrically conductive liner on sidewalls and a bottom of the copper core, a top surface of the wire coplanar with a top surface of the dielectric layer; forming a metal cap on an entire top surface of the copper core; without exposing the substrate to oxygen, forming a dielectric cap over the metal cap, any exposed portions of the liner, and the dielectric layer; and wherein the dielectric cap is an oxygen diffusion barrier and contains no oxygen atoms.

Claims

1. A method comprising:

(a) forming wire embedded in a dielectric layer on a semiconductor substrate, said wire comprising a copper core and an electrically conductive liner on sidewalls and a bottom of said copper core, a top surface of said wire coplanar with a top surface of said dielectric layer;

(b) forming a metal cap on an entire top surface of said copper core;

(c) without exposing said substrate to oxygen, forming a dielectric cap over said metal cap, any exposed portions of said liner, and said dielectric layer; and

wherein said dielectric cap is an oxygen diffusion barrier and contains no oxygen atoms.

2. The method of claim 1, wherein:

(b) and (c) are performed in a same chamber of a first deposition tool without removing said substrate from said chamber;

or

(b) and (c) are performed in a different chambers of a second deposition tool without removing said substrate from said tool.

3. The method of claim 1, wherein said metal cap is formed by either selective chemical vapor deposition or selective atomic layer deposition and said dielectric cap is formed by chemical vapor deposition.

4. The method of claim 1, where in said metal cap is a metal selected from the group consisting of ruthenium, cobalt, titanium, palladium, nickel, gold, iridium, manganese and combinations thereof.

5. The method of claim 1, wherein said dielectric cap comprises silicon nitride, silicon carbide, amorphous silicon carbonitride or combinations thereof.

6. The method of claim 1, further including:

between (b) and (c), (d) without exposing said substrate to oxygen, forming an alloy cap on said metal cap; and

wherein (c) includes forming said dielectric cap on said alloy cap, any exposed regions of said metal cap, any exposed portions of said liner, and said dielectric layer.

7. The method of claim 6, wherein:

(b), (c) and (d) are performed in a same chamber of a first deposition tool without removing said substrate from said chamber;

or

(b) and (d) are performed in a first chamber and (c) is performed in a third chamber of a second deposition tool;

or

(b), (d) and (c) are performed in different chambers of a third deposition tool.

8. The method of claim 6, wherein said metal cap is formed by either selective chemical vapor deposition or selective atomic layer deposition, said alloy cap is formed by either selective chemical vapor deposition or selective atomic layer deposition, and said dielectric cap is formed by chemical vapor deposition.

9. The method of claim 6, wherein said alloy cap comprises RuP, RuB, RuW, RuPW, RuPB, RuBW, RuPBW, CoP, CoB, CoW, CoPW, CoPB, CoBW, CoPBW, MnP, MnB, MnW, MnPW, MnPB, MnBW or MnPBW.

10. The method of claim 6, further including:

between (a) and (b), recessing a top surface of said copper core below said top surface of said dielectric layer.

11. The method of claim 1, further including:

between (a) and (b), recessing a top surface of said copper core below said top surface of said dielectric layer.

12. A structure, comprising:

a wire embedded in a dielectric layer on a semiconductor substrate, said wire comprising a copper core and an electrically conductive liner on sidewalls and a bottom of said copper core, said copper core and said electrically conductive liner exposed at a top surface of said dielectric layer;

a metal cap on an entire top surface of said copper core;

a dielectric cap over said metal cap, on any exposed portions of said liner, and on said dielectric layer; and

wherein an interface between said copper core and said metal layer does not contain oxygen.

13. The structure of claim 12, wherein said dielectric cap is an oxygen diffusion barrier.

14. The structure of claim 12, wherein (i) said metal cap is a metal selected from the group consisting of ruthenium, cobalt, titanium, palladium, nickel, gold, iridium, manganese and combinations thereof and (ii) said dielectric cap comprises silicon nitride, silicon carbide, amorphous silicon carbonitride or combinations thereof.

15. The structure of claim 12, further including:

an alloy cap on said metal cap; and

wherein said dielectric cap is formed on said alloy cap, any exposed regions of said metal cap, any exposed portions of said liner, and said dielectric layer.

16. The structure of claim 15, wherein said alloy cap comprises RuP, RuB, RuW, RuPW, RuPB, RuBW, RuPBW, CoP, CoB, CoW, COPW, CoPB, CoBW, CoPBW, MnP, MnB, MnW, MnPW, MnPB, MnBW or MnPBW.

17. The structure of claim 15, wherein a top surface of said copper core and said electrically conductive liner are coplanar with said top surface of said dielectric layer.

18. The structure of claim 15, wherein a top surface said electrically conductive liner is coplanar with said top surface of said dielectric layer and a top surface of said copper core is recessed below said top surface of said dielectric layer.

19. The structure of claim 12, wherein a top surface of said copper core and said electrically conductive liner are coplanar with said top surface of said dielectric layer.

20. The structure of claim 12, wherein a top surface said electrically conductive liner is coplanar with said top surface of said dielectric layer and a top surface of said copper core is recessed below said top surface of said dielectric layer.

21. A deposition tool comprising:

a load/unload chamber;

a mechanism for transferring a substrate between said load/unload chamber and a deposition chamber, said deposition chamber connected to said load/unload chamber by a port; and

wherein said deposition chamber is (i) configured to selectively form a metal layer on copper by chemical vapor deposition or by atomic layer deposition and (ii) is configured to form a dielectric layer by chemical vapor deposition.

22. The deposition tool of claim 21 wherein said deposition tool is further configured to selectively deposit a metal alloy layer on said metal layer by chemical vapor deposition or by atomic layer deposition

23. A deposition tool, comprising:

a load/unload chamber, first and second deposition chambers connected to said load/unload chamber by respective ports;

a mechanism for transferring a substrate between said first deposition chamber, said second deposition chamber and said load/unload chamber;

wherein said first deposition chamber configured to selectively form a metal layer on copper by chemical vapor deposition or by atomic layer deposition; and

wherein said second deposition chamber is configured to form a dielectric layer by chemical vapor deposition.

24. The deposition tool of claim 23, wherein (i) said first and second deposition chambers are configured for chemical vapor deposition or (ii) said first deposition chamber is configured for atomic layer deposition and said second deposition chamber is configured for chemical vapor deposition.

25. The deposition chamber of claim 23, wherein said first chamber is also configured to form a metal alloy layer on said metal layer by either selective chemical vapor deposition or selective atomic layer deposition.

26. The deposition tool of claim 23, further including:

a third deposition chamber configured to selectively form a metal alloy on a metal; and

wherein (i) said first, second and third deposition chambers are configured for chemical vapor deposition or (ii) said first and third deposition chamber are configured for chemical vapor deposition and said second chamber is configured for atomic layer deposition, or (iii) said second and third deposition chambers are configured chemical vapor deposition and said first chamber is configured for atomic layer deposition, or (iv) said first and second deposition chambers are configured for atomic layer deposition and said third deposition chamber is configured for chemical vapor deposition.