ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS

• US 20110050282A1
• Filed: 11/10/2010
• Published: 03/03/2011
• Est. Priority Date: 08/03/1993
• Status: Active Grant

• Current Assignee: Benjamin S. Ting
• Original Assignee: Benjamin S. Ting
• Inventors: Ting, Benjamin S.
• Granted Patent: US 8,289,047 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs).

Claims

1. A field programmable gate array architecture, comprising:

(a) a first logical cluster having a first span in a first dimension and having a second span in a second dimension, the cluster comprising a plurality of cells, each cell comprising;

an output,

at least one input, and

an input multiplexer coupled to each input;

(b) a first plurality of intraconnect conductors within the first and second spans, wherein the output of each cell in the first logical cluster is selectively coupleable to at least one input multiplexer coupled to each of the other cells in the first logical cluster by traversing a single one of the first plurality of intraconnect conductors;

(c) a second logical cluster having a third span in the first dimension and having a span in the second dimension equal to the second span, the cluster comprising a plurality of cells, each cell having;

an output,

at least one input, and

an input multiplexer coupled to each input;

(d) a second plurality of intraconnect conductors within the second and third spans, wherein the output of each cell in the second logical cluster is selectively coupleable to at least one input multiplexer coupled to each of the other cells in the second logical cluster by traversing a single one of the second plurality of intraconnect conductors;

(e) a third logical cluster having a fourth span in the first dimension and a span in the second dimension equal to the second span, the cluster comprising a plurality of cells, each cell having;

an output,

at least one input, and

an input multiplexer coupled to each input;

(f) a third plurality of intraconnect conductors within the second and fourth spans, wherein the output of each cell in the third logical cluster is selectively coupleable to at least one input multiplexer coupled to each of the other cells in the third logical cluster by traversing a single one of the third plurality of intraconnect conductors;

(g) a fourth logical cluster having a fifth span in the first dimension and a span in the second dimension equal to the second span, the cluster comprising a plurality of cells, each cell having;

an output,

at least one input, and

an input multiplexer coupled to each input;

(h) a fourth plurality of intraconnect conductors within the second and fifth spans, wherein the output of each cell in the fourth logical cluster is selectively coupleable to at least one input multiplexer of each of the other cells in the fourth logical cluster by traversing a single one of the fourth plurality of intraconnect conductors.

2. The field programmable gate array architecture of claim 1, further comprising:

(i) a fifth plurality of routing conductors having a sixth span in the first dimension and a span in the second dimension equal to the second span, wherein the output of each cell in the first logical cluster is selectively coupleable to a plurality of input multiplexers in the second logical cluster; and

(j) a sixth plurality of routing conductors having a seventh span in the first dimension and a span in the second dimension equal to the second span, wherein the output of each cell in the third logical cluster is selectively coupleable to a plurality of input multiplexers in the fourth logical cluster, wherein at least one of the routing conductors in the fifth plurality of conductors is selectively coupleable to at least one of the routing conductors in the sixth plurality of conductors.

3. A programmable logic circuit, comprising:

an input configured to receive a signal into the programmable logic circuit;

a plurality of cells coupled to the input, each of the plurality of cells configured to process the signal;

a first set of routing lines configured to directly couple, through a first set of programmable switches, to the plurality of cells to form logical blocks of cells, wherein input and outputs of cells of logical blocks are programmably coupled to the first set of routing lines; and

a second set of routing lines, configured to couple directly and bidirectionally to the first set of routing lines through a second set of programmable switches, each routing line of the first set of routing lines selectively configured to be a source to drive a routing line of the second set of routing lines through the second set of programmable switches and a sink to receive the signal through the second set of programmable switches from the routing line of the second set of routing lines, wherein a span of the second set of routing lines is longer than a span of the first set of routing lines.

4. The programmable logic circuit of claim 3, wherein the second set of programmable switches comprises components selected from the group consisting of switches, programmable pas sgates and program controlled drivers/receivers.

5. An integrated circuit, comprising:

a first region comprising;

a first plurality of cells located along a first dimension and a second dimension, wherein the first region has a first span along the first dimension and a second span along the second dimension;

a plurality of switches; and

a first plurality of conductors located within the first region, wherein each conductor of the first plurality of conductors to selectively couple to inputs and outputs of cells of the first plurality of cells and conductors of the first plurality of conductors through the plurality of switches and wherein the first plurality of conductors span cells of the first plurality of cells along the first dimension and the second dimension, wherein the first plurality of conductors comprises;

a first conductor having a first span along the first dimension;

a second conductor having a second span along the first dimension;

a third conductor having a third span along the second dimension;

and

a fourth conductor having a fourth span along the second dimension;

wherein the first span of the first region is greater than the first span of the first conductor and the first span of the first conductor is greater than the second span of the second conductor,

wherein the second span of the first region is greater than the third span of the third conductor and the third span of the third conductor is greater than the fourth span of the fourth conductor.

6. The integrated circuit of claim 5, further comprising a second region, located within the first region, having a span along the first dimension, comprising:

a subgroup of cells of the first plurality of cells located in the second region, wherein the span of the second region is less than the second span of the second conductor;

a fifth conductor of the first plurality of conductors located within the second region having a fifth span equal to the span of the second region along the first dimension.