DIVIDE-BY-TWO INJECTION-LOCKED RING OSCILLATOR CIRCUIT

• US 20110050296A1
• Filed: 09/03/2009
• Published: 03/03/2011
• Est. Priority Date: 09/03/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Fagg, Russell J.
• Granted Patent: US 8,487,670 B2
• Time in Patent Office: Days
• US Class Current: 327/118
• CPC Class Codes: H03B 2200/0074 Locking of an oscillator by injecting an input signal directly into the oscillator
• CPC Class Codes: H03B 2200/0078 generating or using signals in quadrature
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors

Abstract

A frequency divider involves a plurality of Injection-locked Ring Oscillators (ILRO). A first ILRO includes a pair of cross-coupled N-channel transistors, a pair of load resistors, an integrating capacitor, and a current injection circuit. The drain of each transistor is coupled to the gate of the other transistor. Each load resistor couples the drain of each transistor to a circuit voltage source. The integrating capacitor couples the sources of each transistor. The current injection circuit alternately opens and closes a path from the source of each transistor to circuit ground in response to an oscillatory input signal of a first frequency. In response, the voltage state at the drain of each transistor is alternately latched and toggled, generating a differential pair of oscillating signals frequency divided by two. A first and second ILRO driven in antiphase generate two differential output signals in phase quadrature.

Claims

1. A frequency divider comprising:

a first Injection-locked Ring Oscillator (ILRO) comprising;

a first cross-coupled transistor pair including a first N-channel transistor and a second N-channel transistor, wherein a drain of the first N-channel transistor is a first output node, wherein a drain of the second N-channel transistor is a second output node, wherein a gate of the first N-channel transistor is coupled to the second output node, and wherein a gate of the second N-channel transistor is coupled to the first output node;

a first capacitor having a first lead coupled to a source of the first N-channel transistor and a second lead coupled to a source of the second N-channel transistor; and

a first current injection circuit having a first lead coupled to the source of the first N-channel transistor, a second lead coupled to the source of the second N-channel transistor, and a first input node.

2. The frequency divider of claim 1, wherein an input signal of a first frequency is present on the first input node of the first current injection circuit, wherein an output signal of a second frequency is present between the first and second output nodes of the first ILRO, and wherein the first frequency is twice the second frequency.

3. The frequency divider of claim 1, wherein the first current injection circuit comprises:

a third N-channel transistor having a source, a drain, and a gate, wherein the drain of the third N-channel transistor is coupled to the source of the first N-channel transistor, wherein the gate of the third N-channel transistor is coupled to the first input node of the first current injection circuit; and

a fourth N-channel transistor having a source, a drain, and a gate, wherein the drain of the fourth N-channel transistor is coupled to the source of the second N-channel transistor, and wherein the gate of the fourth N-channel transistor is coupled to the first input node of the first current injection circuit.

4. The frequency divider of claim 1, further comprising:

a second Injection-locked Ring Oscillator (ILRO) comprising;

a second cross-coupled transistor pair including a third N-channel transistor and a fourth N-channel transistor, wherein a drain of the third N-channel transistor is a third output node, wherein a drain of the fourth N-channel transistor is a fourth output node, wherein a gate of the third N-channel transistor is coupled to the fourth output node, and wherein a gate of the fourth N-channel transistor is coupled to the third output node;

a second capacitor having a first lead coupled to the source of the third N-channel transistor and a second lead coupled to the source of the fourth N-channel transistor; and

a second current injection circuit having a first lead coupled to the source of the third N-channel transistor, a second lead coupled to the source of the fourth N-channel transistor, and a second input node.

5. The frequency divider of claim 4, wherein a differential input signal is present between the first input node of the first current injection circuit and the second input node of the second current injection circuit, wherein an in-phase (I) differential output signal is present between the first and second output nodes of the first ILRO, and wherein a quadrature (Q) differential output signal is present between the third and fourth output nodes of the second ILRO.

6. The frequency divider of claim 1, wherein an input signal is present on the first input node of the first current injection circuit, wherein an in-phase (I) differential output signal is present between the first and second output nodes, and wherein a quadrature (Q) differential output signal is present between the source of the first N-channel transistor and the source of the second N-channel transistor.

7. The frequency divider of claim 1, further comprising:

a second Injection-locked Ring Oscillator (ILRO) having a second input node, a third output node, and a fourth output node; and

a third Injection-locked Ring Oscillator (ILRO) having a third input node, a fifth output node, and a sixth output node, wherein the fifth output node of the third ILRO is coupled to the first input node of the first ILRO, and wherein the sixth output node of the third ILRO is coupled to the second input node of the second ILRO.

8. The frequency divider of claim 7, wherein an input signal of a first frequency is present on the third input node of the third ILRO, wherein an in-phase (I) differential output signal of a second frequency is present between the first and second output nodes of the first ILRO, wherein a quadrature (Q) differential output signal is present between the third and fourth output nodes of the second ILRO, and wherein the first frequency is four times the second frequency.

9. The frequency divider of claim 4, wherein the first ILRO further comprises:

a fifth N-channel transistor having a source, a drain, and a gate, wherein the drain of the fifth N-channel transistor is coupled to the third output node of the second ILRO, and wherein the gate of the fifth N-channel transistor is coupled to the source of the first N-channel transistor via a first Alternating Current (AC) coupling capacitor;

a sixth N-channel transistor having a source, a drain, and a gate, wherein the drain of the sixth N-channel transistor is coupled to the fourth output node of the second ILRO, wherein the gate of the sixth N-channel transistor is coupled to the source of the second N-channel transistor via a second Alternating Current (AC) coupling capacitor, and wherein the source of the fifth N-channel transistor and the source of the sixth N-channel transistor are coupled to a current source.

10. The frequency divider of claim 3, further comprising:

a first load resistor having a first lead and a second lead, wherein the first lead of the first load resistor is coupled to the first output node;

a second load resistor having a first lead and a second lead, wherein the first lead of the second load resistor is coupled to the second output node, and wherein the second lead of the first load resistor and the second lead of the second load resistor are coupled to a supply voltage node, and wherein the source of the third N-channel transistor and the source of the fourth N-channel transistor of the current injection circuit are coupled to a ground node.

11. A frequency divider comprising:

a first Injection-locked Ring Oscillator (ILRO) having a first input lead that receives a first oscillatory signal of a first frequency, a first output lead and a second output lead that output an in-phase (I) differential output signal of a second frequency, wherein the first frequency is twice the second frequency, and wherein the ILRO comprises;

a cross-coupled transistor pair including a first N-channel transistor and a second N-channel transistor, wherein a drain of the first N-channel transistor is coupled to the first output lead, wherein a drain of the second N-channel transistor is coupled to the second output lead;

a capacitor having a first lead coupled to a source of the first N-channel transistor and a second lead coupled to a source of the second N-channel transistor; and

a current injection circuit having a first lead coupled to the source of the first N-channel transistor, a second lead coupled to the source of the second N-channel transistor, and a third lead coupled to the first input lead of the first ILRO.

12. The frequency divider of claim 11 further comprising:

a second ILRO of substantially identical construction to the first ILRO, having a second input lead that receives a second oscillatory signal, a third output lead and a fourth output lead that output a quadrature (Q) differential output signal, wherein the first oscillatory signal and the second oscillatory signal are a differential input signal, and wherein the in-phase (I) signal and the quadrature (Q) signal are approximately ninety degrees out of phase.

13. A method comprising:

latching a voltage present on a first output node of a first Injection-locked Ring Oscillator (ILRO) to a first voltage state in response to a digital high state of a first input signal, wherein a current substantially equal to a circuit supply voltage divided by a first load resistor value flows through a first N-channel transistor of the first ILRO; and

toggling the voltage present on the first output node to a second voltage state in response to a digital low state of the first input signal, wherein the voltage present on the first output node is increased by integrating charge across a first capacitor.

14. The method of claim 13, wherein a circuit ground voltage and the circuit supply voltage are supplied to the first ILRO, and wherein the first voltage state is within one hundred millivolts of the circuit ground voltage and the second voltage state is within fifty millivolts of the circuit supply voltage.

15. The method of claim 13, further comprising:

latching a voltage present on a second output node of the first ILRO to the second voltage state in response to the digital high state of the first input signal, wherein substantially no current flows through a second N-channel transistor of the first ILRO; and

toggling the voltage present on the second output node to the first voltage state in response to the digital low state of the first input signal, wherein the voltage at the second output node is decreased by integrating charge across the first capacitor.

16. The method of claim 15, wherein the first ILRO is a part of a frequency divider circuit.

17. The method of claim 15, further comprising:

receiving a differential output signal present between the first output node and the second output node of the first ILRO.

18. The method of claim 15, further comprising:

latching a voltage present on a third output node of a second ILRO and a voltage present on a fourth output node of the second ILRO in response to a digital high state of a second input signal; and

toggling the voltage present on the third output node of the second ILRO and the voltage present on the fourth output node of the second ILRO in response to a digital high state of the second input signal, wherein the first input signal is approximately one hundred and eighty degrees out of phase with the second input signal.

19. The method of claim 18, further comprising:

latching a voltage present on a fifth output node of a third ILRO and a voltage present on a sixth output node of the third ILRO in response to a digital high state of a third input signal; and

toggling the voltage present on the fifth output node of the third ILRO and the voltage present on the sixth output node of the third ILRO in response to a digital high state of the third input signal, wherein the fifth output node supplies the first input signal to the first ILRO and the sixth output node supplies the second input signal to the second ILRO.

20. The method of claim 18, further comprising:

inverting a voltage signal present on a third voltage node of the first ILRO, thereby generating an inverted voltage signal; and

transmitting the inverted voltage signal to the first output node of the second ILRO.

21. A frequency divider circuit comprising:

a conductor that receives a first input signal onto the frequency divider circuit; and

means for frequency dividing the input signal by a fixed integer thereby generating an in-phase (I) differential output signal, wherein the means includes a first capacitor, and wherein the first capacitor at least in part increases a voltage swing of the I differential output signal.

22. The frequency divider circuit of claim 21, wherein the means is an Injection-Locked Ring Oscillator (ILRO), wherein the ILRO includes a cross-coupled transistor pair including a first N-channel transistor and a second N-channel transistor, and wherein a first lead of the first capacitor is coupled to a source of the first N-channel transistor and a second lead of the first capacitor is coupled to a source of the second N-channel transistor.

23. The frequency divider circuit of claim 21, further comprising:

a second conductor that receives a second input signal onto the frequency divider circuit, wherein the first input signal and the second input signal are a differential input signal, and wherein the means frequency divides the second input signal thereby generating a quadrature (Q) differential output signal, and wherein the means also includes a second capacitor, and wherein the second capacitor at least in part increases the voltage swing of the Q differential output signal.