LOW-CAPACITANCE ELECTROSTATIC DISCHARGE PROTECTION DIODES

• US 20110050335A1
• Filed: 11/05/2010
• Published: 03/03/2011
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Poon, Steven S., Maloney, Timothy J.
• Granted Patent: US 8,304,807 B2
• Time in Patent Office: Days
• US Class Current: 327/565
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0814 Diodes only

Abstract

A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Claims

1. An input buffer comprising:

a pad to receive an input signal;

a first diode comprising a first terminal coupled to the pad, and a second terminal coupled to receive a first supply voltage; and

a second diode comprising a first terminal coupled to receive a second supply voltage, and a second terminal coupled to the pad,

wherein the first and second diodes include a lower level metal layer and an adjacent higher level metal layer with corresponding lower level metal lines and corresponding adjacent higher level metal lines respectively, and wherein the lower level metal lines and the adjacent higher level metal lines being parallel to one another in a diode region of each of the first and second diodes.

2. The input buffer of claim 1, wherein one of the first and second diodes comprises:

a first supply diffusion region to receive either a first or second supply voltage, the first supply diffusion region having a width that is larger than a minimum width associated with supply diffusion regions for a process technology on which the first and second diodes are manufactured.

3. The input buffer of claim 2, wherein one of the first and second diodes comprises:

a first pad diffusion region to couple to the pad, the first pad diffusion region having a width equal to a minimum width associated with pad diffusion regions for the process technology on which the first and second diodes are manufactured.

4. The input buffer of claim 3, wherein the lower level metal layer to provide the lower level metal lines as interconnects for the first pad diffusion region and the first supply diffusion region in the diode regions of each of the first and second diodes.

5. The input buffer of claim 3, wherein the adjacent higher level metal layer comprises:

a first portion to couple the first pad diffusion region to the pad; and

a second portion to couple the first supply diffusion region to either one of the first supply voltage or the second supply voltage.

6. The input buffer of claim 5, wherein the first and second portions of the adjacent higher level metal layer having the adjacent higher level metal lines to extend across less than 50% of the diode region from opposite sides of the diode region of either one of the first and second diodes.

7. The input buffer of claim 5, wherein the first and second portions of the adjacent higher level metal layer having the adjacent higher level metal lines to extend across an entire diode region of either one of the first and second diodes.

8. The input buffer of claim 2, wherein the width of the first supply diffusion region is 50% wider than the minimum width associated with supply diffusion regions for the process technology on which the first and second diodes are manufactured.

9. The input buffer of claim 1, wherein the first terminal of the first diode is for coupling to the pad via a pad diffusion region of the diode region of the first diode, and wherein the second terminal of the first diode is for coupling to a supply diffusion region of the diode region of the first diode, the supply diffusion region to receive the first supply voltage.

10. The input buffer of claim 1, wherein the first terminal of the second diode is for coupling to a supply diffusion region of the diode region of the second diode, the supply diffusion region to receive the second supply voltage, and wherein the second terminal of the second diode is for coupling to the pad via a pad diffusion region of the diode region of the second diode.

11. The input buffer of claim 1, wherein first supply voltage is a ground supply voltage, and wherein the second supply voltage is a power supply voltage.

12. The input buffer of claim 1, wherein one of the first and second diodes comprises:

pad diffusion regions coupled to the pad; and

supply diffusion regions coupled to receive the respective supply voltage, wherein the supply diffusion regions have a width which is wider than a minimum width associated with supply diffusion regions for a process technology on which the first and second diodes are manufactured, and

wherein the pad diffusion regions have a width which is a minimum width associated with pad diffusion regions for the process technology on which the first and second diodes are manufactured.

13. The input buffer of claim 12, wherein the width of the supply diffusion regions for one of the diodes is 50% wider than the minimum width for the supply diffusion regions.

14. The input buffer of claim 12, wherein the adjacent higher level metal layer of one the diodes comprises:

a first portion to couple the corresponding pad diffusion regions to the pad; and

a second portion to couple the corresponding supply diffusion regions to receive the respective supply voltage, wherein the adjacent higher level metal lines of the first and second portions extending less than 50% across the diode region from opposite sides of the diode region.

15. The input buffer of claim 12, wherein the adjacent higher level metal layer of one of the diodes comprises:

a first portion to couple the pad diffusion regions to the pad; and

a second portion to couple the supply diffusion regions to receive the respective supply voltage, each portion having the adjacent higher level metal lines that extend across an entire width of the diode region from opposite sides of the diode region of one of the diodes.

16. An apparatus comprising:

a pad to receive an input signal;

an input buffer coupled to the pad to receive the input signal;

a first diode comprising a first terminal coupled to the pad and the input buffer, and a second terminal coupled to receive a first supply voltage; and

a second diode comprising a first terminal coupled to receive a second supply voltage, and a second terminal coupled to the pad and the input buffer,

wherein the first and second diodes include a lower level metal layer and an adjacent higher level metal layer with corresponding lower level metal lines and corresponding adjacent higher level metal lines respectively, and wherein the lower level metal lines and the adjacent higher level metal lines being parallel to one another in a diode region of each of the first and second diodes.

17. The apparatus of claim 16, wherein one of the first and second diodes comprises:

a first supply diffusion region to receive either a first or second supply voltage, the first supply diffusion region having a width that is larger than a minimum width associated with supply diffusion regions for a process technology on which the first and second diodes are manufactured; and

a first pad diffusion region to couple to the pad, the first pad diffusion region having a width equal to a minimum width associated with pad diffusion regions for the process technology on which the first and second diodes are manufactured.

18. The apparatus of claim 17, wherein the lower level metal layer to provide the lower level metal lines as interconnects for the first pad diffusion region and the first supply diffusion region in the diode regions of each of the first and second diodes.

19. The apparatus of claim 17, wherein the adjacent higher level metal layer comprises:

a first portion to couple the first pad diffusion region to the pad; and

a second portion to couple the first supply diffusion region to either one of the first supply voltage or the second supply voltage.

20. The apparatus of claim 19, wherein the first and second portions of the adjacent higher level metal layer having the adjacent higher level metal lines to extend across less than 50% of the diode region from opposite sides of the diode region of either one of the first and second diodes.

21. The apparatus of claim 19, wherein the first and second portions of the adjacent higher level metal layer having the adjacent higher level metal lines to extend across an entire diode region of either one of the first and second diodes.

22. The apparatus of claim 17, wherein the width of the first supply diffusion region is 50% wider than the minimum width associated with supply diffusion regions for the process technology on which the first and second diodes are manufactured.