DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING A SERIALIZED QUANTIZER OUTPUT

• US 20110050472A1
• Filed: 08/31/2009
• Published: 03/03/2011
• Est. Priority Date: 08/31/2009
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Melanson, John L.
• Granted Patent: US 7,903,010 B1
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: H03M 3/424 the quantiser being a multiple bit one
• CPC Class Codes: H03M 3/474 using time-division multiplexing

Abstract

A delta-sigma analog-to-digital converter (ADC) having a serialized quantizer output has a data rate greater than a quantization rate of the delta-sigma modulator, but less than a bit rate determined by the product of the number of bits required to represent the input to a feedback digital-to-analog converter and the quantization rate. Additional information can be encoded in the serial bit stream by selection among redundant codes based on the value of the additional information. The serial bit stream may encode differences between successive quantizer output samples and the additional information may include the absolute value of the quantizer output, synchronization information and/or framing information for distinguishing data corresponding to multiple ADC input channels.

Claims

14. An analog-to-digital converter, comprising:

a quantizer for generating a digital output from an analog input signal; and

an output encoder for generating a data output of the analog-to-digital converter from the digital output of the quantizer, wherein the data output represents changes in the digital output as a sequence of codes in the data output, and wherein the sequence of codes extends over a set of codes including at least one redundant code, whereby one value of the changes in the digital output is represented by at least two codes, and wherein a pattern of the at least two codes in the data output represents an indication of an absolute level of the digital output.

15. A decoder circuit for receiving and decoding a serial bit stream representing output values of an analog-to-digital conversion, the decoder circuit comprising:

a receiver for receiving the serial bit stream, wherein the serial bit stream encodes the output values of the analog-to-digital conversion along with additional information by using redundant codes to express at least one output level of the analog-to-digital conversion; and

a decoder for decoding the serial bit stream to obtain the output values, wherein the decoder checks a sequence of codes within the serial bit stream for error by examining a sequence of the redundant codes.

16. The decoder circuit of claim 15, wherein the serial bit stream encodes changes in an output of a quantizer that performs the analog-to-digital conversion, wherein the additional information represents an absolute level of the output of the quantizer, wherein the decoder further obtains the absolute level of the output of the quantizer from the serial bit stream.

17. The decoder circuit of claim 15, wherein the serial bit stream represents oversampled values of the analog-to-digital conversion and wherein the decoder circuit further comprises a decimation filter having an input coupled to an output of the decoder for generating an output from the oversampled values.

18-1. The method of claim 18, wherein the converting generates the serial bit stream to encode differences between sequential values of the result of the quantizing at the quantization rate.