METHOD AND CIRCUIT FOR CALIBRATING PHASE, AND SIGNAL PROCESSING APPARATUS HAVING THE SAME

• US 20110050474A1
• Filed: 07/14/2010
• Published: 03/03/2011
• Est. Priority Date: 09/01/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Byoung Joong
• Granted Patent: US 8,344,309 B2
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled

Abstract

A method for calibrating a phase include comparing a phase of an in-phase output signal and a phase of a quadrature-phase output signal and generating a digital code corresponding to a comparison result, and controlling the phase of the in-phase output signal in response to quadrature-phase differential input signals and the digital code, and controlling the phase of the quadrature-phase output signal in response to in-phase differential input signals and the digital code, to make a phase difference between the in-phase output signal and the quadrature-phase output signal 90°.

Claims

1. A method for calibrating a phase, the method comprising:

comparing a phase of an in-phase output signal and a phase of a quadrature-phase output signal and generating a digital code corresponding to a comparison result; and

controlling the phase of the in-phase output signal in response to quadrature-phase differential input signals and the digital code, and controlling the phase of the quadrature-phase output signal in response to in-phase differential input signals and the digital code, to make a phase difference between the in-phase output signal and the quadrature-phase output signal 90°

.

2. A circuit for calibrating phases of signals output from a local oscillator, the circuit comprising:

a first buffer for outputting an in-phase output signal;

a second buffer for outputting a quadrature-phase output signal;

a code generation circuit for comparing a phase of the in-phase output signal and a phase of the quadrature-phase output signal and generating a digital code corresponding to a comparison result; and

a phase calibration circuit for controlling the phase of the in-phase output signal in response to quadrature-phase differential input signals and the digital code, and controlling the phase of the quadrature-phase output signal in response to in-phase differential input signals and the digital code, to make the phase difference between the in-phase output signal and the quadrature-phase output signal 90°

.

3. The circuit of claim 2, wherein the code generation circuit comprises:

a phase detector for detecting the phase difference between the in-phase output signal and the quadrature-phase output signal and generating a first detection signal and a second detection signal;

a low pass filter for performing low pass filtering on each of the first and second detection signals and generating a first filter signal and a second filter signal;

a comparator for comparing the first and second filter signals and outputting a comparison signal; and

a code generator for generating the digital code according to a clock signal and the comparison signal.

4. The circuit of claim 3, wherein the code generator generates the digital code that is up-counted or down-counted according to a level of the comparison signal and the clock signal.

5. The circuit of claim 3, wherein the code generator generates a calibration control signal to control an operation of the comparator based on a change of the level of the comparison signal.

6. The circuit of claim 2, wherein the phase calibration circuit comprises:

a first digital-to-analog converter for controlling the phase of the in-phase output signal in response to the quadrature-phase differential input signals and the digital code; and

a second digital-to-analog converter for controlling the phase of the quadrature-phase output signal in response to the in-phase differential input signals and the digital code.

7. The circuit of claim 6, wherein the first digital-to-analog converter comprises a plurality of first digital-to-analog units to control the phase of the in-phase output signal, each of the plurality of first digital-to-analog units being connected in parallel to output terminals of the first buffer,

the second digital-to-analog converter comprises a plurality of second digital-to-analog units to control the phase of the quadrature-phase output signal, each of the plurality of second digital-to-analog units being connected in parallel to output terminals of the second buffer, and

each of the plurality of first digital-to-analog units and each of the plurality of second digital-to-analog units are enabled/disabled based on the most significant bit (MSB) of the digital code.

8. A wireless signal processing apparatus comprising:

a first buffer for outputting an in-phase output signal;

a second buffer for outputting a quadrature-phase output signal;

a first mixer for mixing an output signal of the first buffer and an in-phase baseband output signal;

a second mixer for mixing an output signal of the second buffer and a quadrature-phase baseband output signal;

a code generation circuit for comparing a phase of the in-phase output signal and a phase of the quadrature-phase output signal and generating a digital code corresponding to a comparison result; and

a phase calibration circuit for controlling the phase of the in-phase output signal in response to quadrature-phase differential input signals and the digital code, and controlling the phase of the quadrature-phase output signal in response to in-phase differential input signals and the digital code, to make a phase difference between the in-phase output signal and the quadrature-phase output signal 90°

.

9. The wireless signal processing apparatus of claim 8, wherein the code generation circuit comprises:

a phase detector for detecting the phase difference between the in-phase output signal and the quadrature-phase output signal and generating a first detection signal and a second detection signal;

a low pass filter for performing low pass filtering on each of the first and second detection signals and generating a first filter signal and a second filter signal;

a comparator for comparing the first and second filter signals and outputting a comparison signal; and

a code generator for generating the digital code according to a clock signal and the comparison signal.

10. The wireless signal processing apparatus of claim 9, wherein the code generator generates a calibration control signal based on a change of a level of the comparison signal, and the wireless signal processing apparatus further comprises a switch for transmitting the in-phase output signal and the quadrature-phase output signal to the code generation circuit in response to the calibration control signal.