LOW VOLTAGE DIFFERENTIAL SIGNAL OUTPUT STAGE

• US 20110050681A1
• Filed: 11/23/2009
• Published: 03/03/2011
• Est. Priority Date: 08/27/2009
• Status: Active Grant

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Hsin, Tung-Cheng, Chen, Hsiang-Chih
• Granted Patent: US 8,466,911 B2
• Time in Patent Office: Days
• US Class Current: 345/214
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2370/14 Use of low voltage differential signaling [LVDS] for display data communication
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/008 Clock recovery

Abstract

A low voltage differential signal (LVDS) output stage including a display signal digital circuit, a data parallel-to-serial (P2S) circuit and a transmitting circuit is provided. The display signal digital circuit generates a display signal and a display clock signal synchronous to each other according to a first frequency multiplication clock signal. The data P2S circuit samples the display signal according to a second frequency multiplication clock signal, so as to generate a serial data signal and a serial clock signal. The first frequency multiplication clock signal and the second frequency multiplication clock signal have a relationship of frequency multiplication. The data P2S circuit includes an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second frequency multiplication clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second frequency multiplication clock signal.

Claims

1. A low voltage differential signal (LVDS) output stage, comprising:

a display signal digital circuit, generating a display signal and a display clock signal synchronous to each other according to a first clock signal having a first frequency;

a data parallel-to-serial (P2S) circuit, sampling the display signal according to a second clock signal having a second frequency, so as to generate a serial data signal and a serial clock signal, wherein the first frequency of the first clock signal and the second frequency of the second clock signal have a multiplication relationship, the data P2S circuit comprises an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second clock signal; and

a transmitting circuit, connected to the data P2S circuit, for outputting the serial data signal and the serial clock signal to serve as outputs of the LVDS output stage.

2. The LVDS output stage as claimed in claim 1, further comprising a frequency multiplier for generating the first clock signal and the second clock signal according to a reference clock.

3. The LVDS output stage as claimed in claim 2, wherein the reference clock is a clock signal provided to the display signal digital circuit by a front stage device.

4. The LVDS output stage as claimed in claim 2, wherein the reference clock is generated by a system comprising the LVDS output stage.

5. The LVDS output stage as claimed in claim 1, wherein the first clock signal and the second clock signal are provided by a frequency multiplier of a system comprising the LVDS output stage.

6. The LVDS output stage as claimed in claim 1, wherein the data P2S circuit comprises:

a pipeline delay stage, receiving the second clock signal and the display clock signal, and sampling the display clock signal according to the second clock signal, so as to generate a reset signal;

a frequency divider, receiving the second clock signal, outputting the serial clock signal after performing a frequency dividing operation, and outputting a load signal; and

a P2S unit, sampling the display signal to generate the serial data signal, and outputting the serial data signal in response to the load signal,

wherein the reset signal is used for resetting a stage of the frequency divider to change a phase of the load signal and a phase of the serial clock signal output from the frequency divider, so that the load signal is capable of correctly triggering the P2S unit to output the serial data signal.

7. The LVDS output stage as claimed in claim 1, wherein the adjustment structure comprises:

a pipeline delay stage, receiving the second clock signal and the display clock signal, and sampling the display clock signal according to the second clock signal, so as to generate a quantified signal;

a determining circuit, connected to the pipeline delay stage, for determining a positive edge section of the display clock signal to determine a phase difference between the load signal and the display clock signal, so as to adjust a shift signal; and

a frequency divider, receiving a signal, outputting the serial clock signal after performing a frequency dividing operation, and outputting a load signal,

wherein the signal is generated according to the second clock signal and the shift signal.

8. The LVDS output stage as claimed in claim 7, wherein the determining circuit receives a vertical sync signal and a data enable signal in the display signal to adjust a time section for triggering the load signal, so that the time section falls within a data blank time section of the display signal.

9. A low voltage differential signal (LVDS) output stage, comprising:

a frequency multiplier, generating a first clock signal having a first frequency and a second clock signal having a second frequency according to a reference clock, wherein the first frequency and the second frequency have a multiplication relationship;

a display signal digital circuit, generating a display signal and a display clock signal synchronous to each other according to the first clock signal;

a data parallel-to-serial (P2S) circuit, sampling the display signal according to the second clock signal and the display clock signal, so as to generate a serial data signal and a serial clock signal, wherein the data P2S circuit further feeds back a phase adjusting signal to the frequency multiplier for adjusting a phase of the generated first clock signal, so as to adjust a phase of the display clock signal; and

a transmitting circuit, connected to the data P2S circuit, for outputting the serial data signal and the serial clock signal to serve as outputs of the LVDS output stage.

10. The LVDS output stage as claimed in claim 9, wherein the frequency multiplier adjusts the phase of the display clock signal for a delay amount according to the phase adjusting signal of the data P2S circuit, so as to achieve a phase lock between the display clock signal and the second clock signal transmitted to the data P2S circuit.

11. The LVDS output stage as claimed in claim 9, wherein the reference clock is a clock signal provided to the display signal digital circuit by a front stage device.

12. The LVDS output stage as claimed in claim 9, wherein the reference clock is generated by a system comprising the LVDS output stage.

13. The LVDS output stage as claimed in claim 9, wherein the data P2S circuit receives a vertical sync signal and a data enable signal in the display signal to adjust a time for outputting the serial data signal, so that the time falls within a data blank time section of the display signal.

14. A low voltage differential signal (LVDS) output stage, comprising:

a display signal digital circuit, receiving a display signal, and generating a display signal and a display clock signal synchronous to each other;

a display phase-locked loop (PLL), receiving the display clock signal, and outputting a first clock signal and a second clock signal synchronous to each other after a phase locking operation, wherein the first frequency and the second frequency have a multiplication relationship;

a data parallel-to-serial (P2S) circuit, sampling the display signal according to the second clock signal, so as to generate a serial data signal and a serial clock signal; and

a transmitting circuit, connected to the data P2S circuit, for outputting the serial data signal and the serial clock signal to serve as outputs of the LVDS output stage.

15. The LVDS output stage as claimed in claim 14, wherein an adjustment structure of the data P2S circuit comprises:

a pipeline delay stage, receiving the second clock signal and the display clock signal, and sampling the display clock signal according to the second clock signal, so as to generate a reset signal;

a frequency divider, receiving the second clock signal, outputting the serial clock signal after performing a frequency dividing operation, and outputting a load signal; and

a parallel-to-serial (P2S) unit, sampling the display signal to generate the serial data signal, and outputting the serial data signal in response to the load signal,

wherein the reset signal is used for resetting a stage of the frequency divider to change a phase of the load signal and a phase of the serial clock signal output from the frequency divider, so that the load signal is capable of correctly triggering the P2S unit to output the serial data signal.

16. A low voltage differential signal (LVDS) output stage, comprising:

a display signal digital circuit, receiving a display signal, and generating a display signal and a first clock signal synchronous to each other;

a display phase-locked loop (PLL), receiving the first clock signal, and outputting a second clock signal after a phase locking operation, wherein the first frequency and the second frequency s have a multiplication relationship;

a data parallel-to-serial (P2S) circuit with a phase correction function, sampling the display signal according to the second clock signal to generate a serial data signal and a serial clock signal, the data P2S circuit with the phase correction function comprising an adjustment structure for adjusting phases of the first clock signal and the second clock signal, and accordingly adjusting the serial clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second clock signal; and

a transmitting circuit, connected to the data P2S circuit, for outputting the serial data signal and the serial clock signal to serve as outputs of the LVDS output stage.

17. The LVDS output stage as claimed in claim 16, wherein the adjustment structure of the data P2S circuit comprises:

a pipeline delay stage, receiving the second clock signal and the first clock signal, and sampling the first clock signal according to the second clock signal, so as to generate a quantified signal;

a determining circuit, connected to the pipeline delay stage, for determining a positive edge section of the first clock signal, and outputting a shift signal; and

a frequency divider, receiving a signal, outputting the serial clock signal after performing a frequency dividing operation, and outputting a load signal, wherein the signal is generated according to the second clock signal and the shift signal, and the determining circuit generates the shift signal according to the load signal fed back by the frequency divider and the quantified signal, wherein the determining circuit determines a phase difference between the load signal and the display clock signal, so as to adjust the shift signal.

18. The LVDS output stage as claimed in claim 17, wherein the determining circuit receives a vertical sync signal and a data enable signal in the display signal to adjust a time section for triggering the load signal, so that the time section falls within a data blank time section of the display signal.