LOW VOLTAGE DIFFERENTIAL SIGNAL OUTPUT STAGE
First Claim
1. A low voltage differential signal (LVDS) output stage, comprising:
- a display signal digital circuit, generating a display signal and a display clock signal synchronous to each other according to a first clock signal having a first frequency;
a data parallel-to-serial (P2S) circuit, sampling the display signal according to a second clock signal having a second frequency, so as to generate a serial data signal and a serial clock signal, wherein the first frequency of the first clock signal and the second frequency of the second clock signal have a multiplication relationship, the data P2S circuit comprises an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second clock signal; and
a transmitting circuit, connected to the data P2S circuit, for outputting the serial data signal and the serial clock signal to serve as outputs of the LVDS output stage.
1 Assignment
0 Petitions
Accused Products
Abstract
A low voltage differential signal (LVDS) output stage including a display signal digital circuit, a data parallel-to-serial (P2S) circuit and a transmitting circuit is provided. The display signal digital circuit generates a display signal and a display clock signal synchronous to each other according to a first frequency multiplication clock signal. The data P2S circuit samples the display signal according to a second frequency multiplication clock signal, so as to generate a serial data signal and a serial clock signal. The first frequency multiplication clock signal and the second frequency multiplication clock signal have a relationship of frequency multiplication. The data P2S circuit includes an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second frequency multiplication clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second frequency multiplication clock signal.
-
Citations
18 Claims
-
1. A low voltage differential signal (LVDS) output stage, comprising:
-
a display signal digital circuit, generating a display signal and a display clock signal synchronous to each other according to a first clock signal having a first frequency; a data parallel-to-serial (P2S) circuit, sampling the display signal according to a second clock signal having a second frequency, so as to generate a serial data signal and a serial clock signal, wherein the first frequency of the first clock signal and the second frequency of the second clock signal have a multiplication relationship, the data P2S circuit comprises an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second clock signal; and a transmitting circuit, connected to the data P2S circuit, for outputting the serial data signal and the serial clock signal to serve as outputs of the LVDS output stage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A low voltage differential signal (LVDS) output stage, comprising:
-
a frequency multiplier, generating a first clock signal having a first frequency and a second clock signal having a second frequency according to a reference clock, wherein the first frequency and the second frequency have a multiplication relationship; a display signal digital circuit, generating a display signal and a display clock signal synchronous to each other according to the first clock signal; a data parallel-to-serial (P2S) circuit, sampling the display signal according to the second clock signal and the display clock signal, so as to generate a serial data signal and a serial clock signal, wherein the data P2S circuit further feeds back a phase adjusting signal to the frequency multiplier for adjusting a phase of the generated first clock signal, so as to adjust a phase of the display clock signal; and a transmitting circuit, connected to the data P2S circuit, for outputting the serial data signal and the serial clock signal to serve as outputs of the LVDS output stage. - View Dependent Claims (10, 11, 12, 13)
-
-
14. A low voltage differential signal (LVDS) output stage, comprising:
-
a display signal digital circuit, receiving a display signal, and generating a display signal and a display clock signal synchronous to each other; a display phase-locked loop (PLL), receiving the display clock signal, and outputting a first clock signal and a second clock signal synchronous to each other after a phase locking operation, wherein the first frequency and the second frequency have a multiplication relationship; a data parallel-to-serial (P2S) circuit, sampling the display signal according to the second clock signal, so as to generate a serial data signal and a serial clock signal; and a transmitting circuit, connected to the data P2S circuit, for outputting the serial data signal and the serial clock signal to serve as outputs of the LVDS output stage. - View Dependent Claims (15)
-
-
16. A low voltage differential signal (LVDS) output stage, comprising:
-
a display signal digital circuit, receiving a display signal, and generating a display signal and a first clock signal synchronous to each other; a display phase-locked loop (PLL), receiving the first clock signal, and outputting a second clock signal after a phase locking operation, wherein the first frequency and the second frequency s have a multiplication relationship; a data parallel-to-serial (P2S) circuit with a phase correction function, sampling the display signal according to the second clock signal to generate a serial data signal and a serial clock signal, the data P2S circuit with the phase correction function comprising an adjustment structure for adjusting phases of the first clock signal and the second clock signal, and accordingly adjusting the serial clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second clock signal; and a transmitting circuit, connected to the data P2S circuit, for outputting the serial data signal and the serial clock signal to serve as outputs of the LVDS output stage. - View Dependent Claims (17, 18)
-
Specification