Tuner and Front-end Circuit Thereof

• US 20110051014A1
• Filed: 07/28/2010
• Published: 03/03/2011
• Est. Priority Date: 09/02/2009
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MStar Semiconductor Incorporated (MediaTek, Inc.)
• Inventors: Chou, Chung-Yun, Wang, Fucheng, Lu, Yi
• Granted Patent: US 8,836,447 B2
• Time in Patent Office: Days
• US Class Current: 348/731
• CPC Class Codes: H03J 3/06 Arrangements for obtaining constant bandwidth or gain throughout tuning range or ranges
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only

Abstract

A tuner includes a plurality of paths, and at least one of the paths includes a front-end filter circuit, an amplifier, and a trace filter. The trace filter includes a varactor and an inductor, which are coupled to an output end of the amplifier. Further, the amplifier and the varactor of the tuner are packed in a complementary metal-oxide semiconductor (CMOS) chip.

Claims

1. A tuning circuit, comprising:

a transformer, for converting a single-end signal to a differential signal;

a first path, comprising a first filter circuit; and

a second path, comprising a second filter circuit;

wherein, the first filter circuit and the second filter circuit are electrically connected to an output end of the transformer.

2. The tuning circuit as claimed in claim 1, wherein the first filter circuit is a low-pass filter and the second filter circuit is either a high-pass filter or a band-pass filter.

3. The tuning circuit as claimed in claim 1, further comprises a third path, comprising a third filter circuit;

wherein

the first filter circuit comprises;

a first inductor, directly coupled to the output end of the transformer; and

a first capacitor, coupled between the first inductor and a reference voltage;

the second filter circuit comprises;

a second capacitor, directly coupled to the output end of the transformer; and

a second inductor, coupled between the second capacitor and the reference voltage; and

the third filter circuit comprises;

a third inductor, directly coupled to the output end of the transformer; and

a third capacitor, coupled between the third inductor and an output end of the third filter circuit.

4. The tuning circuit as claimed in claim 3, wherein the first path further comprises a first switch coupled between the first inductor and the reference voltage;

the second path further comprises a second switch coupled between the second capacitor and the reference voltage; and

the third channel further comprises a third switch coupled between the third inductor and the reference voltage.

5. The tuning circuit as claimed in claim 4, wherein when the tuning circuit is selecting a channel, only one of the first switch, the second switch, and the third switch is open.

6. The tuning circuit as claimed in claim 4, wherein the first switch, the second switch, and the third switch are packed in a single chip, and the first inductor, the second inductor, and the third inductor are externally connected to the chip.

7. The tuning circuit as claimed in claim 6, wherein the third capacitor is packed in the single chip, and the first capacitor and the second capacitor are externally connected to the chip.

8. A tuner, comprising:

a first path;

a second path, comprising;

a front-end filter circuit;

a differential amplifier, coupled to the front-end filter circuit; and

a trace filter, comprising;

a varactor, coupled to two output ends of the differential amplifier, and

an inductor, coupled to the varactor in parallel;

wherein the amplifier and the varactor are integrated in a complementary mental-oxide semiconductor (CMOS) chip.

9. The tuner as claimed in claim 8, further comprising:

a transformer for converting a single-end signal to a differential signal;

the first path comprises a first filter circuit; and

the second path comprises a second filter circuit;

wherein the first filter circuit and the second filter circuit are electrically connected to an output end of the transformer.

10. The tuner as claimed in claim 8, further comprising an attenuator, coupled between the front-end filter circuit and the differential amplifier.

11. The tuner as claimed in claim 8, wherein the inductor is packed in the CMOS chip.

12. The tuner as claimed in claim 8, further comprising:

a frequency generator, coupled to an input end of the trace filter, for providing an adjustment signal to the trace filter, wherein the adjustment signal has a first frequency and the trace filter filters the adjustment signal to generate a filtered adjustment signal;

a signal intensity detecting unit, coupled to the trace filter, for detecting an intensity value of the filtered adjustment signal; and

an adjusting unit, coupled to the signal intensity detecting unit, for adjusting a capacitance value of the varactor according to the intensity value of the filtered adjustment signal.

13. The tuner as claimed in claim 12, wherein the adjusting unit constantly adjusts the capacitance value of the varactor until the intensity value of the filtered adjustment signal detected by the signal intensity detecting unit is determined as a maximum intensity value.

14. The tuner as claimed in claim 12, wherein the frequency generator selects the first frequency from a plurality of predetermined frequencies to generate the adjustment signal, and the plurality of predetermined frequencies is a plurality of center frequencies corresponding to a plurality of television (TV) channels of a TV system.

15. A tuner, comprising:

a plurality of paths, at least one of the paths comprising;

a front-end filter circuit;

an amplifier, coupled to the front-end filter circuit; and

a trace filter, comprising;

a varactor, coupled to a ground end and an output end of the amplifier; and

an inductor, coupled to the varactor in parallel;

wherein, the amplifier and the varactor are integrated in a single chip, and the inductor is externally connected to the chip.

16. The tuner as claimed in claim 15, wherein the front-end filter circuit further comprising:

a first filter circuit path, comprising a first filter circuit; and

a second filter circuit path, comprising a second filter circuit;

wherein the first filter circuit and the second filter circuit are directly electrically connected to a node.

17. The tuner as claimed in claim 15, further comprising an attenuator, coupled between the front-end filter circuit and the amplifier.

18. The tuner as claimed in claim 15, wherein the path further comprising:

a frequency generator, coupled to an input end of the trace filter, for providing an adjustment signal to the trace filter, wherein the adjustment signal comprises a first frequency, the trace filter filters the adjustment signal to generate a filtered adjustment signal;

a signal intensity detecting unit, coupled to the trace filter, for detecting an intensity value of the filtered adjustment signal; and

an adjusting unit, coupled to the signal intensity detecting unit, for adjusting a capacitance value of the varactor according to the intensity value of the filtered adjustment signal.

19. The tuner as claimed in claim 18, wherein the adjusting unit constantly adjusts the capacitance value of the varactor until the intensity value of the filtered adjustment signal detected by the signal intensity detecting unit is determined as a maximum intensity value.

20. The tuner as claimed in claim 18, wherein the frequency generator selects the first frequency from a plurality of predetermined frequencies to generate the adjustment signal, and the plurality of predetermined frequencies is a plurality of center frequencies corresponding to a plurality of TV channels of a TV system.