SMALL UNIT INTERNAL VERIFY READ IN A MEMORY DEVICE

• US 20110051523A1
• Filed: 09/02/2009
• Published: 03/03/2011
• Est. Priority Date: 09/02/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tamada, Satoru, Manabe, Tetsuji
• Granted Patent: US 8,077,532 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory block). Mask data is loaded into a third dynamic data cache of three dynamic data caches. The expected data is loaded into a second data cache. After a read operation of programmed columns of memory cells, the read data is compared to the expected data and error bit indicators are stored in the second data cache in the error bit locations. The second data cache is masked with the mask data so that only those error bits that are unmasked are counted. If the number of unmasked error bit indicators is greater than a threshold, the memory block is marked as unusable.

Claims

1. A method for a verify read in a memory device, the method comprising:

performing a read operation of a plurality of columns of memory cells of a grouping of columns of the memory device;

masking a subset of the plurality of read columns of memory cells; and

determining if the grouping of columns is unusable in response to only those columns of the grouping of columns that are not masked.

2. The method of claim 1 wherein the plurality of columns of memory cells comprise a first page of data.

3. The method of claim 1 wherein the grouping of columns is a memory block.

4. The method of claim 1 and further comprising storing mask data, for masking the subset of the plurality of read columns of memory cells, into a data cache of the memory device.

5. The method of claim 1 wherein determining if the grouping of columns is unusable comprises comparing read data from the read operation to expected data that was programmed into the plurality of columns of memory cells.

6. The method of claim 2 wherein performing the read operation is performed on each page of data of the grouping of columns of the memory device prior to determining if the grouping of columns is unusable.

7. The method of claim 1 wherein masking the subset of the plurality of read columns comprises masking a different data cache associated with each column of the subset of the plurality of read columns.

8. A method for a verify read in a memory device, the method comprising:

programming expected data to a grouping of memory cells;

storing mask data to a first plurality of caches, each cache bit associated with a different column of the grouping of memory cells;

copying the mask data from the first plurality of caches to a second plurality of caches, each cache bit associated with a different column of the grouping of memory cells;

storing the expected data to the first plurality of caches;

copying the mask data from the second plurality of caches to a third plurality of caches, each cache bit associated with a different column of the grouping of memory cells;

reading data from a subset of the grouping of memory cells;

comparing the read data with the expected data;

storing, in response to comparing, an error indication in bit locations of the second plurality of caches for each column having an error bit;

masking particular bit locations of the second plurality of data caches in response to the mask data;

comparing a reference current to a judged current; and

marking the grouping of memory cells unusable in response to comparing the reference current to the judged current.

9. The method of claim 8 wherein comparing the read data with the expected data comprises comparing the second plurality of caches to the first plurality of caches.

10. The method of claim 8 wherein the first plurality of caches are secondary data caches, the second plurality of caches are primary data caches, and the third plurality of caches are dynamic data caches.

11. The method of claim 8 wherein the error indication is a logical error bit indicator.

12. The method of claim 8 wherein comparing the reference current to the judged current comprises:

turning on a first quantity of transistors indicative of a criteria of allowed error bits to generate the reference current;

turning on a second quantity of transistors indicative of a quantity of defective memory cells that are not masked to generate the judged current; and

marking the grouping of memory cells unusable if the judged current is greater than the reference current.

13. A memory device comprising:

an array of memory cells organized in columns and rows;

a plurality of data caches coupled to the array of memory cells, each column associated with a different bit location of each data cache; and

memory control circuitry coupled to the array of memory cells, the memory control circuitry is configured to execute a read operation of a group of columns of the array of memory cells, the memory control circuitry further configured to store an error indication for each data cache bit location associated with a column of the group of columns having an error, mask a subset of the data cache bit locations, and determine if the group of columns is unusable in response to only those bit locations that are unmasked.

14. The memory device of claim 13 wherein the array of memory cells is comprised of a NAND architecture of non-volatile memory cells.

15. The memory device of claim 13 wherein the plurality of data caches are organized as primary data caches, secondary data caches, and first, second, and third dynamic data caches.

16. The memory device of claim 13 wherein the plurality of data caches are coupled through a multiplexing circuit such that the plurality of data caches are coupled to only one of odd memory cell columns or even memory cell columns at a time.

17. The memory device of claim 16 and further comprising a precharge circuit and a temporary data cache coupled to the array of memory cells through the multiplexing circuit.

18. The memory device of claim 15 wherein the memory control circuitry is further configured to refresh the mask data stored in the third dynamic data cache.

19. The memory device of claim 15 wherein the memory control circuitry is further configured to store expected data in the secondary data cache, read data in the primary data cache, and mask data in the third dynamic data cache.

20. The memory device of claim 19 wherein the memory control circuitry is further configured to use the mask data in the third dynamic data cache to mask particular bit locations of the primary data cache.