POWER SAVING METHOD AND CIRCUIT THEREOF FOR A SEMICONDUCTOR MEMORY

• US 20110051525A1
• Filed: 11/09/2010
• Published: 03/03/2011
• Est. Priority Date: 10/04/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lin, Yung-Feng
• Granted Patent: US 8,174,924 B2
• Time in Patent Office: Days
• US Class Current: 365/185.27
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated.

Claims

1. An operating method for a semiconductor memory having a well region, comprising steps of:

receiving a plurality of address codes; and

activating a well boost process to boost the well region when a currently received address code is different from a last received address code, otherwise maintaining a voltage of the well region.

2. A method according to claim 1, wherein the semiconductor memory is a Flash memory.

3. A method according to claim 1, wherein the plurality of address codes are of a binary format.

4. A method according to claim 1, further comprising a step of activating a first boost process to activate an internal read operation in the semiconductor memory for maintaining the voltage of the well region, when the currently received address code is the same as the last received address code.

5. A method according to claim 1, further comprising a step of activating an address trigger detection process to determine whether the currently received address code is different from the last received address code.

6. A method according to claim 1, wherein the well region boosted by the well boost process has a type different from that of a present well region.

7. An operating circuit for a semiconductor memory having a well region, comprising:

a receiving circuit receiving a plurality of address codes; and

an activating circuit activating a well boost process to boost the well region when a currently received address code is different from a last received address code, otherwise activating maintaining a voltage of the well region.

8. An operating circuit according to claim 7, wherein the semiconductor memory is a Flash memory.

9. An operating circuit according to claim 7, wherein the plurality of address codes are binary.

10. An operating circuit according to claim 7, wherein the receiving circuit has an address trigger detection process for determining whether the currently received address code is different from the last received address code.

11. An operating circuit according to claim 7, wherein the well region boosted by the well boost process has a type different from that of a present well region.

12. An operating circuit according to claim 7, wherein the activating circuit activates a first boost process to activate an internal read operation in the semiconductor memory for maintaining the voltage of the well region

13. An operating method for a semiconductor memory having a well region, comprising steps of:

receiving a plurality of address codes; and

activating a well boost process to boost the well region when a currently received address code is different from a last received address code.

14. A method according to claim 13, wherein the semiconductor memory is a Flash memory.

15. A method according to claim 13, wherein the plurality of address codes are of a binary format.

16. A method according to claim 13, further comprising a step of activating a first boost process to activate an internal read operation in the semiconductor memory for maintaining the voltage of the well region, when the currently received address code is the same as the last received address code.

17. A method according to claim 13, further comprising a step of activating an address trigger detection process to determine whether the currently received address code is different from the last received address code.

18. A method according to claim 13, wherein the well region boosted by the well boost process has a type different from that of a present well region.