NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20110051527A1
• Filed: 03/17/2010
• Published: 03/03/2011
• Est. Priority Date: 09/01/2009
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Mikajiri, Yoshimasa, Oota, Shigeto, Kito, Masaru, Kirisawa, Ryouhei
• Granted Patent: US 8,320,182 B2
• Time in Patent Office: Days
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory unit; and

a control unit,

the memory unit including a first memory string, a first wiring, a second memory string, and a second wiring,

the first memory string including a first memory cell group and a first select transistor,

the first memory cell group including a plurality of first memory transistors connected in series,

each of the plurality of first memory transistors including a channel formed in a first semiconductor layer, including a first control gate, and allowing data of the each of the plurality of first memory transistors to be electrically rewritten,

the first select transistor being provided on one end side of the first memory cell group, including a channel formed in the first semiconductor layer, and including a first select gate,

the first wiring being connected to the first semiconductor layer on a side of the first select transistor opposite to the first memory cell group,

the second memory string including a second memory cell group and a second select transistor,

the second memory cell group including a plurality of second memory transistors connected in series,

each of the plurality of second memory transistors including a channel formed in a second semiconductor layer electrically isolated from the first semiconductor layer, including a control gate electrically connected to the first control gate, and allowing data of the each of the plurality of second memory transistors to be electrically rewritten,

the second select transistor being provided on one end side of the second memory cell group, including a channel formed in the second semiconductor layer, and including a select gate connected to the first select gate,

the second wiring being connected to the second semiconductor layer on a side of the second select transistor opposite to the second memory cell group,

in a selective erase operation for performing at least one of injection of a hole into a charge retention layer of a selected cell transistor in the selective erase operation of the first memory transistors and extraction of an electron from the charge retention layer of the selected cell transistor in the selective erase operation, the control unit being configured to;

apply a first voltage to the first wiring,

apply a second voltage lower than the first voltage to a selected cell gate of the first control gate of the selected cell transistor in the selective erase operation,

apply a third voltage not higher than the first voltage and higher than the second voltage to a non-selected cell gate in the selective erase operation of the first control gate of the first memory transistors other than the selected cell transistor in the selective erase operation,

apply the first voltage or a fourth voltage not higher than the first voltage and not lower than the third voltage to the first select gate, and

apply the second voltage or a fifth voltage higher than the second voltage and not higher than the third voltage to the second wiring or set the second wiring in a floating state.

2. The device according to claim 1, wherein the second voltage is 0 volts, and the third voltage is substantially equal to the fourth voltage.

3. The device according to claim 1, further comprising:

a substrate,

the first semiconductor layer and the second semiconductor layer aligning in a direction perpendicular to a major surface of the substrate.

4. The device according to claim 1, wherein in a selective write operation for performing at least one of injection of an electron into a charge retention layer of a selected cell transistor in the selective write operation of the first memory transistors and extraction of a hole from the charge retention layer of the selected cell transistor in the selective write operation, the control unit is configured to:

apply the first voltage to a selected cell gate of the first control gate of the selected cell transistor in the selective write operation,

apply the second voltage to the first wiring,

apply a voltage higher than the second voltage and not higher than the third voltage to a non-selected cell gate in the selective write operation of the first control gate of the first memory transistors other than the selected cell transistor in the selective write operation,

apply a voltage higher than the second voltage and not higher than the third voltage to the first select gate, and

apply a voltage higher than the second voltage and not higher than the third voltage to the second wiring.

5. The device according to claim 1, wherein in a read operation for reading data written in a selected cell transistor in the read operation of the first memory transistors, the control unit is configured to:

apply a reading bit line voltage not higher than the fifth voltage and higher than the second voltage to the first wiring,

apply a sense voltage varied between the fifth voltage and the second voltage to a selected cell gate of the first control gate of the selected cell transistor in the read operation,

apply the fifth voltage to a non-selected cell gate in the read operation of the first control gate of the first memory transistors other than the selected cell transistor in the read operation,

apply the fifth voltage to the first select gate, and

apply the second voltage to the second wiring.

6. The device according to claim 1, wherein

the memory unit further includes a third memory string,

the third memory string includes a third memory cell group and a third select transistor,

the third memory cell group includes a plurality of third memory transistors connected in series,

each of the plurality of third memory transistors includes a channel formed in a third semiconductor layer electrically isolated from the first semiconductor layer and the second semiconductor layer, includes a second control gate, and allows data of the each of the plurality of third memory transistors to be electrically rewritten,

the third select transistor is provided on one end side of the third memory cell group, includes a channel formed in the third semiconductor layer, and includes a second select gate,

the first wiring is connected to the third semiconductor layer on a side of the third select transistor opposite to the third memory cell group, and

in the selective erase operation, the control unit is configured to:

apply a sixth voltage lower than the third voltage to the second control gate of the third memory transistors, and

apply a seventh voltage lower than the third voltage to the second select gate.

7. The device according to claim 6, wherein the sixth voltage and the seventh voltage are 0 volts.

8. The device according to claim 6, wherein in a selective write operation for performing at least one of injection of an electron into a charge retention layer of a selected cell transistor in the selective write operation of the first memory transistors and extraction of a hole from the charge retention layer of the selected cell transistor in the selective write operation, the control unit is configured to:

apply a voltage lower than the third voltage to the second control gate of the third memory transistors, and

apply a voltage lower than the third voltage to the second select gate.

9. The device according to claim 6, wherein in a read operation for reading data written in a selected cell transistor in the read operation of the first memory transistors, the control unit is configured to:

apply the second voltage to the second control gate of the third memory transistors, and

apply the second voltage to the second select gate.

10. The device according to claim 1, wherein

the memory unit further includes a first other wiring and a second other wiring,

the first memory string further includes a first other memory cell group, a first other select transistor, and a first connecting portion transistor,

the first other select transistor is provided on a side of the first memory cell group opposite to the first select transistor, includes a channel formed in the first semiconductor layer, and includes a first other select gate,

the first connecting portion transistor is provided between the first memory cell group and the first other select transistor, includes a channel formed in the first semiconductor layer, and includes a first connecting portion gate,

the first other memory cell group is provided between the first other select transistor and the first connecting portion transistor and includes a plurality of first other memory transistors connected in series,

each of the plurality of first other memory transistors includes a channel formed in the first semiconductor layer, includes a first other control gate, and allows data of the each of the plurality of first other memory transistors to be electrically rewritten,

the first other wiring is connected to the first semiconductor layer on a side of the first other select transistor opposite to the first other memory cell group,

the second memory string further includes a second other memory cell group, a second other select transistor, and a second connecting portion transistor,

the second other select transistor is provided on a side of the second memory cell group opposite to the second select transistor, includes a channel formed in the second semiconductor layer, and includes a second other select gate,

the second connecting portion transistor is provided between the second memory cell group and the second other select transistor, includes a channel formed in the second semiconductor layer, and includes a connecting portion gate electrically connected to the first connecting portion gate,

the second other memory cell group is provided between the second other select transistor and the second connecting portion transistor and includes a plurality of second other memory transistors connected in series,

each of the plurality of second other memory transistors includes a channel formed in the second semiconductor layer, includes a second other control gate electrically connected to the first other control gate, and allows data of the each of the plurality of second other memory transistors to be electrically rewritten,

the second other wiring is connected to the second semiconductor layer on a side of the second other select transistor opposite to the second other memory cell group, and

in the selective erase operation, the control unit is further configured to:

apply the fifth voltage or the second voltage to the first other wiring or set the first other wiring in a floating state,

apply the third voltage to the first other control gate,

apply an eighth voltage lower than the third voltage to the first other select gate,

apply a ninth voltage lower than the first voltage and higher than the second voltage to the first connecting portion gate,

apply the fifth voltage, the first voltage, or the second voltage to the second other wiring or set the second other wiring in a floating state,

apply the sixth voltage or the third voltage to the second control gate,

apply the eighth voltage to the second select gate, and

apply the eighth voltage to the second other select gate.

11. The device according to claim 10, wherein the eighth voltage is substantially equal to the second voltage, and the ninth voltage is substantially equal to the third voltage.

12. The device according to claim 10, further comprising:

a substrate,

the first semiconductor layer and the second semiconductor layer aligning in a direction perpendicular to a major surface of the substrate.

13. The device according to claim 10, wherein in a selective write operation for performing at least one of injection of an electron into a charge retention layer of a selected cell transistor in the selective write operation of the first memory transistors and extraction of a hole from the charge retention layer of the selected cell transistor in the selective write operation, the control unit is configured to:

apply the second voltage to the first wiring,

apply the first voltage to a selected cell gate of the first control gate of the selected cell transistor in the selective write operation,

apply the fifth voltage to a non-selected cell gate in the selective write operation of the first control gate of the first memory transistors other than the selected cell transistor in the selective write operation,

apply the fifth voltage to the first select gate, the second wiring, the first other control gate, and the first connecting portion gate,

apply the fifth voltage or the second voltage to the first other wiring or set the first other wiring in a floating state,

apply the second voltage to the first other select gate, the second other wiring, the second select gate, the second other select gate, and the second connecting portion gate, and

apply the second voltage or the fifth voltage to the second control gate.

14. The device according to claim 10, wherein in a read operation for reading data written in a selected cell transistor in the read operation of the first memory transistors, the control unit is configured to:

apply a reading bit line voltage not higher than the fifth voltage and higher than the second voltage to the first wiring,

apply a sense voltage varied between the fifth voltage and the second voltage to a selected cell gate of the first control gate of the selected cell transistor in the read operation,

apply the fifth voltage to a non-selected cell gate in the read operation of the first control gate of the first memory transistors other than the selected cell transistor in the read operation,

apply the fifth voltage to the first select gate, the first other control gate, the first other select gate, and the first connecting portion gate, and

apply the second voltage to the second wiring, the first other wiring, the second other wiring, the second control gate, the second select gate, the second other select gate, and the second connecting portion gate.

15. A nonvolatile semiconductor memory device comprising:

a memory unit; and

a control unit,

the memory unit including a first memory string, a first wiring, a first other wiring, and a first base wiring,

the first memory string including a first memory cell group, a first other memory cell group, a first select transistor, a first other select transistor, and a first connecting portion transistor,

the first memory cell group including a plurality of first memory transistors connected in series,

each of the plurality of first memory transistors including a channel formed in a first semiconductor layer provided in contact with a first base semiconductor layer, including a first control gate, and allowing data of the each of the plurality of first memory transistors to be electrically rewritten,

the first select transistor being provided on one end side of the first memory cell group, including a channel formed in the first semiconductor layer, and including a first select gate,

the first other select transistor being provided on a side of the first memory cell group opposite to the first select transistor, including a channel formed in the first semiconductor layer, and including a first other select gate,

the first connecting portion transistor being provided between the first memory cell group and the first other select transistor, including a channel formed in the first semiconductor layer, and including a first connecting portion gate,

the first other memory cell group being provided between the first other select transistor and the first connecting portion transistor and including a plurality of first other memory transistors connected in series,

each of the plurality of first other memory transistors including a channel formed in the first semiconductor layer, including a first other control gate, and allowing data of the each of the plurality of first other memory transistors to be electrically rewritten,

the first wiring being connected to the first semiconductor layer on a side of the first select transistor opposite to the first memory cell group,

the first other wiring being connected to the first semiconductor layer on a side of the first other select transistor opposite to the first other memory cell group,

the first base wiring being connected to the first base semiconductor layer,

in a selective erase operation for performing at least one of injection of a hole into a charge retention layer of a selected cell transistor in the selective erase operation of the first memory transistors and extraction of an electron from the charge retention layer of the selected cell transistor in the selective erase operation, the control unit being configured to;

apply a first voltage to the first wiring and the first other wiring or set the first wiring and the first other wiring in a floating state,

apply a second voltage lower than the first voltage to a selected cell gate of the first control gate of the selected cell transistor in the selective erase operation,

apply a third voltage lower than the first voltage and higher than the second voltage to a non-selected cell gate in the selective erase operation of the first control gate of the first memory transistors other than the selected cell transistor in the selective erase operation,

apply the third voltage to the first other control gate,

apply a tenth voltage lower than the first voltage and higher than the second voltage to the first select gate and the first other select gate,

apply an eleventh voltage lower than the first voltage and higher than the second voltage to the first connecting portion gate, and

apply the first voltage to the first base wiring.

16. The device according to claim 15, wherein the second voltage is 0 volts, and the tenth voltage and the eleventh voltage are substantially equal to the third voltage.

17. The device according to claim 15, wherein

the memory unit further includes a second memory string,

the second memory string includes a second memory cell group, a second other memory cell group, a second select transistor, a second other select transistor, and a second connecting portion transistor,

the second memory cell group includes a plurality of second memory transistors connected in series,

each of the plurality of second memory transistors includes a channel formed in a second semiconductor layer provided in contact with a second base semiconductor layer and electrically isolated from the first semiconductor layer, includes a second control gate, and allows data of the each of the plurality of second memory transistors to be electrically rewritten,

the second select transistor is provided on one end side of the second memory cell group, includes a channel formed in the second semiconductor layer, and includes a second select gate,

the second other select transistor is provided on a side of the second memory cell group opposite to the second select transistor, includes a channel formed in the second semiconductor layer, and includes a second other select gate,

the second connecting portion transistor is provided between the second memory cell group and the second other select transistor, includes a channel formed in the second semiconductor layer, and includes a second connecting portion gate,

the second other memory cell group is provided between the second other select transistor and the second connecting portion transistor and includes a plurality of second other memory transistors connected in series,

each of the plurality of second other memory transistors includes a channel formed in the second semiconductor layer, includes a second other control gate, and allows data of the each of the plurality of second other memory transistors to be electrically rewritten,

the first wiring is further connected to the second semiconductor layer on a side of the second select transistor opposite to the second memory cell group,

the first other wiring is further connected to the second semiconductor layer on a side of the second other select transistor opposite to the second other memory cell group,

the first base wiring is further connected to the second base semiconductor layer, and

in the selective erase operation, the control unit is further configured to:

apply the third voltage to the second control gate and the second other control gate,

apply the tenth voltage to the second select gate and the second other select gate, and

apply the eleventh voltage to the second connecting portion gate.

18. The device according to claim 17, wherein

the memory unit further includes a third memory string, a second wiring, a second other wiring, and a second base wiring,

the third memory string includes a third memory cell group, a third other memory cell group, a third select transistor, a third other select transistor, and a third connecting portion transistor,

the third memory cell group includes a plurality of third memory transistors connected in series,

each of the plurality of third memory transistors includes a channel formed in a third semiconductor layer provided in contact with a third base semiconductor layer and electrically isolated from the first semiconductor layer and the second semiconductor layer, is connected to the first control gate, and allows data of the each of the plurality of third memory transistors to be electrically rewritten,

the third select transistor is provided on one end side of the third memory cell group, includes a channel formed in the third semiconductor layer, and is connected to the first select gate,

the third other select transistor is provided on a side of the third memory cell group opposite to the third select transistor, includes a channel formed in the third semiconductor layer, and is connected to the first other select gate,

the third connecting portion transistor is provided between the third memory cell group and the third other select transistor, includes a channel formed in the third semiconductor layer, and is connected to the first connecting portion gate,

the third other memory cell group is provided between the third other select transistor and the third connecting portion transistor and includes a plurality of third other memory transistors connected in series,

each of the plurality of third other memory transistors includes a channel formed in the third semiconductor layer, is connected to the first other control gate, and allows data of each of the plurality of third other memory transistors to be electrically rewritten,

the second wiring is connected to the third semiconductor layer on a side of the third select transistor opposite to the third memory cell group,

the second other wiring is connected to the third semiconductor layer on a side of the third other select transistor opposite to the third other memory cell group,

the second base wiring is connected to the third base semiconductor layer, and

in the selective erase operation, the control unit is further configured to:

apply a twelfth voltage lower than the first voltage and higher than the second voltage to the second wiring and the second other wiring or set the second wiring and the second other wiring in the floating state, and

apply a thirteenth voltage lower than the first voltage and higher than the second voltage to the second base wiring or set the second base wiring in the floating state.

19. The device according to claim 18, wherein in a selective write operation for performing at least one of injection of an electron into a charge retention layer of a selected cell transistor in the selective write operation of the first memory transistors and extraction of a hole from the charge retention layer of the selected cell transistor in the selective write operation, the control unit is configured to:

apply the second voltage to the first wiring, the first other select gate, and the first base wiring,

apply a fifth voltage higher than the second voltage and not higher than the third voltage to the first select gate and the first connecting portion gate,

apply the first voltage to a selected cell gate of the first control gate of the selected cell transistor in the selective write operation,

apply the fifth voltage to a non-selected cell gate in the selective write operation of the first control gate of the first memory transistors other than the selected cell transistor in the selective write operation,

apply the second voltage or the fifth voltage to the first other wiring, the second other wiring, the second select gate, the second other select gate, the second base wiring, and the second connecting portion gate or set the first other wiring, the second other wiring, the second select gate, the second other select gate, the second base wiring, and the second connecting portion gate in the floating state,

apply the fifth voltage to the second wiring or set the second wiring in the floating state, and

apply the second voltage or the fifth voltage to the second control gate and the second other control gate.

20. The device according to claim 18, wherein in a read operation for reading data written in a selected cell transistor of the first memory transistors, the control unit is configured to:

apply a reading bit line voltage not higher than a fifth voltage and higher than the second voltage to the first wiring, the fifth voltage being higher than the second voltage and not higher than the third voltage,

apply a sense voltage varied between the fifth voltage and the second voltage to a selected cell gate of the first control gate of the selected cell transistor in the read operation,

apply the fifth voltage to a non-selected cell gate in the read operation of the first control gate of the first memory transistors other than the selected cell transistor in the read operation,

apply the fifth voltage to the first select gate, the first other control gate, the first other select gate, and the first connecting portion gate, and

apply the second voltage to the second wiring, the first base wiring, the first other wiring, the second other wiring, the second control gate, the second other control gate, the second select gate, the second other select gate, the second connecting portion gate, and the second base wiring.