SHORT AND LONG TRAINING FIELDS
First Claim
1. An integrated circuit, comprising logic configured to:
- generate a packet comprising a short training field as part of a synchronization header and a long training field as part of the synchronization header;
use the packet for communication in a wireless network.
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Accused Products
Abstract
A method includes receiving a first plurality of symbols comprising complex portions. The method further includes applying conjugate symmetry to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions. The method further includes transforming the second plurality of symbols using an inverse fast Fourier transform, producing a third plurality of symbols. The method further includes interpolating the third plurality of symbols, generating a short training field comprising at least one real portion of the third plurality of symbols, generating a long training field comprising at least one real portion of the third plurality of symbols, and transmitting the short training field and long training field in a WPAN.
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Citations
20 Claims
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1. An integrated circuit, comprising logic configured to:
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generate a packet comprising a short training field as part of a synchronization header and a long training field as part of the synchronization header; use the packet for communication in a wireless network. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit, comprising logic configured to:
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receive a packet comprising a short training field as part of a synchronization header and a long training field as part of the synchronization header; use the packet for communication in a wireless network. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A device, comprising:
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a processor; a memory coupled to the processor; wherein the processor generates a packet comprising a short training field as part of a synchronization header and a long training field as part of the synchronization header; wherein the device uses the packet for communication in a wireless network. - View Dependent Claims (15, 16, 17, 18)
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19. A machine-readable storage medium comprising executable instructions that, when executed, cause one or more processors to:
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receive a first plurality of symbols comprising real portions and complex portions; apply conjugate symmetry to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions; transform the second plurality of symbols using an inverse fast Fourier transform, producing a third plurality of symbols; generate a short training field comprising at least one real portion of the third plurality of symbols; negate one or more repetitions of a group of bits in the short training field. - View Dependent Claims (20)
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Specification