SHORT AND LONG TRAINING FIELDS

• US 20110051747A1
• Filed: 08/25/2010
• Published: 03/03/2011
• Est. Priority Date: 08/31/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: SCHMIDL, Timothy M., BATRA, Anuj, HOSUR, Srinath
• Granted Patent: US 8,553,730 B2
• Time in Patent Office: Days
• US Class Current: 370/474
• CPC Class Codes: H04L 27/2613 Structure of the reference signals
• CPC Class Codes: H04L 27/2634 Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation
• CPC Class Codes: H04W 4/80 Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• CPC Class Codes: H04W 56/001 Synchronization between nodes

Abstract

A method includes receiving a first plurality of symbols comprising complex portions. The method further includes applying conjugate symmetry to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions. The method further includes transforming the second plurality of symbols using an inverse fast Fourier transform, producing a third plurality of symbols. The method further includes interpolating the third plurality of symbols, generating a short training field comprising at least one real portion of the third plurality of symbols, generating a long training field comprising at least one real portion of the third plurality of symbols, and transmitting the short training field and long training field in a WPAN.

Claims

1. An integrated circuit, comprising logic configured to:

generate a packet comprising a short training field as part of a synchronization header and a long training field as part of the synchronization header;

use the packet for communication in a wireless network.

2. The integrated circuit of claim 1, wherein the long training field comprises values [0, −

1, −

1, 1, −

1, 1, 1, −

1, −

1, 1, 1, −

1, −

1, 1, 0, 0, 0, 0, 0, 1, −

1, 1, −

1, 1, 1, 1, 1, 1, 1, 1, 1, −

1] for tones [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, −

16, −

15, −

14, −

13, −

12, −

11, −

10, −

9, −

8, −

7, −

6, −

5, −

4, −

3, −

2, −

1], respectively, wherein the values of 1 or −

1 are adjustable based on a scaling factor.

3. The integrated circuit of claim 1, wherein the short training field comprises a complex portion, wherein the long training field comprises a complex portion, wherein the short training field has a peak-to-average power ratio below 2.248 dB.

4. The integrated circuit of claim 1, comprising logic configured to negate one or more final repetitions of a group of bits in the short training field.

5. The integrated circuit of claim 1, wherein the short training field comprises a complex portion, wherein the long training field comprises a complex portion, wherein the long training field has a peak-to-average power ratio below 3.17 dB.

6. The integrated circuit of claim 1, wherein the short training field comprises values [0, 0, 0, 0, −

1, 0, 0, 0, 1, 0, 0, 0, −

1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0] for tones [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, −

16, −

15, −

14, −

13, −

12, −

11, −

10, −

9, −

8, −

7, −

6, −

5, −

4, −

3, −

2, −

1], respectively, wherein the values of 1 or −

1 are adjustable based on a scaling factor.

7. An integrated circuit, comprising logic configured to:

receive a packet comprising a short training field as part of a synchronization header and a long training field as part of the synchronization header;

use the packet for communication in a wireless network.

8. The integrated circuit of claim 7, wherein automatic gain control calculations are based on the short training field.

9. The integrated circuit of claim 7, wherein boundary detection is based on the short training field.

10. The integrated circuit of claim 7, wherein coarse frequency offset estimation is based on the short training field, and wherein fine frequency offset estimation is based on the long training field.

11. The integrated circuit of claim 7, wherein integer frequency offset estimation is based on the long training field.

12. The integrated circuit of claim 7, wherein fast Fourier transform placement is based on the long training field.

13. The integrated circuit of claim 7, wherein channel estimation is based on the long training field.

14. A device, comprising:

a processor;

a memory coupled to the processor;

wherein the processor generates a packet comprising a short training field as part of a synchronization header and a long training field as part of the synchronization header;

wherein the device uses the packet for communication in a wireless network.

15. The device of claim 14, wherein the short training field comprises a complex portion, wherein the long training field comprises a complex portion, wherein the long training field has a peak-to-average power ratio below 3.17 dB.

16. The device of claim 14, wherein the long training field comprises values [0, −

1, −

1, 1, −

1, 1, 1, −

1, −

1, 1, 1, −

1, −

1, 1, 0, 0, 0, 0, 0, 1, −

1, 1, −

1, 1, 1, 1, 1, 1, 1, 1, 1, −

1] for tones [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, −

16, −

15, −

14, −

13, −

12, −

11, −

10, −

9, −

8, −

7, −

6, −

5, −

4, −

3, −

2, −

1], respectively, wherein the values of 1 or −

1 are adjustable based on a scaling factor.

17. The device of claim 14, wherein the short training field comprises values [0, 0, 0, 0, −

1, 0, 0, 0, 1, 0, 0, 0, −

1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0] for tones [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, −

16, −

15, −

14, −

13, −

12, −

11, −

10, −

9, −

8, −

7, −

6, −

5, −

4, −

3, −

2, −

1], respectively, wherein the values of 1 or −

1 are adjustable based on a scaling factor.

18. The device of claim 14, wherein the short training field comprises and a complex portion, wherein the long training field comprises a complex portion, wherein the short training field has a peak-to-average power ratio below 2.248 dB.

19. A machine-readable storage medium comprising executable instructions that, when executed, cause one or more processors to:

receive a first plurality of symbols comprising real portions and complex portions;

apply conjugate symmetry to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions;

transform the second plurality of symbols using an inverse fast Fourier transform, producing a third plurality of symbols;

generate a short training field comprising at least one real portion of the third plurality of symbols;

negate one or more repetitions of a group of bits in the short training field.

20. The storage medium of claim 19, wherein the one or more processors are further caused to

generate a long training field comprising at least one real portion of the third plurality of symbols;

transmit the short training field and long training field in a wireless network.