Spread spectrum clock generating circuit
First Claim
1. A spread spectrum clock generating circuit, comprisingan external PLL;
- andan internal PLL,wherein the external PLL comprises a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider, each of them connecting successively, wherein the frequency divider is connected to the phase detector in order to form an external loop;
the internal PLL comprises the phase detector, the low-pass filter and the voltage-controlled oscillator of the external PLL, each of them connecting successively, wherein the output terminal of the voltage-controlled oscillator is connected with a counter, and the output terminal of the counter is connected to an input of the oscillator in order to form an internal loop.
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Abstract
A spread spectrum generating circuit comprises an external PLL and an internal PLL. The external PLL comprises a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider, each of them connecting successively. The frequency divider is connected to the phase detector in order to form an external loop. The internal PLL comprises the phase detector, the low-pass filter and the voltage-controlled oscillator of the external PLL, each of them connecting successively. An output terminal of the voltage-controlled oscillator connects with a counter, and the output terminal of the counter connects to an input of the oscillator in order to form an internal loop. The present invention is compatible with the conventional ones, and has lower design risk and higher circuit reliability; compared with the general circuit, it has drastically reduced the area and power consumption, which allows more flexible design and meets more demands.
5 Citations
7 Claims
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1. A spread spectrum clock generating circuit, comprising
an external PLL; - and
an internal PLL, wherein the external PLL comprises a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider, each of them connecting successively, wherein the frequency divider is connected to the phase detector in order to form an external loop; the internal PLL comprises the phase detector, the low-pass filter and the voltage-controlled oscillator of the external PLL, each of them connecting successively, wherein the output terminal of the voltage-controlled oscillator is connected with a counter, and the output terminal of the counter is connected to an input of the oscillator in order to form an internal loop. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification