System and Method for Managing Multiple Independent Graphics Sources in an Information Handling System

• US 20110052142A1
• Filed: 08/28/2009
• Published: 03/03/2011
• Est. Priority Date: 08/28/2009
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Juenger, Randall E., Sultenfuss, Andrew T.
• Granted Patent: US 8,218,940 B2
• Time in Patent Office: Days
• US Class Current: 386/232
• CPC Class Codes: G06F 3/1431 using a single graphics controller
• CPC Class Codes: G06F 3/1438 using more than one graphics controller
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2340/0485 Centering horizontally or vertically
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 2370/045 using multiple communication channels, e.g. parallel and serial
• CPC Class Codes: G09G 2370/20 Details of the management of multiple sources of image data
• CPC Class Codes: G09G 5/005 Adapting incoming signals to the display format of the display terminal
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H04N 21/4122 additional display device, e.g. video projector digital output for controlling a plurality of local displays G06F3/1423
• CPC Class Codes: H04N 21/4143 embedded in a Personal Computer [PC]
• CPC Class Codes: H04N 21/4402 involving reformatting operations of video signals for household redistribution, storage or real-time display details of conversion of video standards at pixel level H04N7/01; video transcoding H04N19/40; adapting incoming signals to the display format of the display terminal G09G5/005; media handling at the source in data packet switching networks H04L65/764
• CPC Class Codes: H04N 21/4436 Power management, e.g. shutting down unused components of the receiver power management in computer systems G06F1/3203; hibernate or awake process in computer systems G06F9/4418
• CPC Class Codes: H04N 21/4622 Retrieving content or additional data from different sources, e.g. from a broadcast channel and the Internet web site content organization and management for information retrieval from the Internet G06F16/958; transmission by internet of broadcast information H04H60/82; stock exchange data over packet-switching network H04L12/1804; push services including data channel over packet-switching network H04L12/1859
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 5/765 Interface circuits between an apparatus for recording and another apparatus

Abstract

An information handling system includes a video processor that provides a first video signal in a first video format; a display that receives a second video signal in a second video format; and another display that receives a third video signal in a third video format. The first, second, and third video formats are all different from each other. The information handling system also includes a mid-stream frame buffer that stores video information from the first, second, and third video signals, and a video selector coupled to the mid-stream frame buffer the video processor and the displays. The video selector converts the First video signal into the second and third video signals and couples the video processor to a selected display.

Claims

1. An information handling system comprising:

a first video processor including a first video output operable to provide a first video signal in accordance with a first video format;

a first display including a first video input operable to receive a second video signal in accordance with a second video format, wherein the second video format is different from the first video format;

a second display including a second video input operable to receive a third video signal in accordance with a third video format, wherein the third video format is different from the first and second video formats;

a mid-stream frame buffer operable to store a selected one of a first video information associated with the first video signal, a second video information associated with the second video signal, or a third video information associated with the third video signal; and

a video selector coupled to;

the mid-stream frame buffer;

the first video output;

the first video input; and

the second video input;

wherein the video selector is operable to;

convert the first video signal into the second video signal;

convert the first video signal into the third video signal; and

couple the first video output to a selected one of the first video input or the second video input.

2. The information handling system of claim 1 wherein further:

the first video processor includes a second video output operable to provide a fourth video signal in accordance with a fourth video format, wherein the fourth video format is different from the first, second, and third video formats;

the mid-stream frame buffer is operable to store a selection of a fourth video information associated with the fourth video signal;

the video selector is coupled to the second video output, and is operable to;

convert the fourth video signal into the second video signal;

convert the fourth video signal into the third video signal; and

couple the fourth video output to a selected one of the first video input or the second video input.

3. The information handling system of claim 2 further comprising:

a second video processor including a third video output operable to provide a fifth video signal in accordance with a fifth video format, wherein the fifth video format is different from the first, second, third, and fourth video formats; and

wherein the video selector is coupled to the second video processor, and is operable to;

convert the fifth video signal into the second video signal;

convert the fifth video signal into the third video signal; and

couple the third video output to a selected one of the first video input or the second video input.

4. The information handling system of claim 3 wherein the video selector is further operable to send the video information from the first, second, or third video output to the mid-stream frame buffer.

5. The information handling system of claim 4 in response to sending the video information to the frame buffer, the information handling system is operable to operate the video processor associated with the selected video output in a low power mode.

6. The information handling system of claim 3 wherein the video selector is further operable to send the video information from the first or second video input to the mid-stream frame buffer.

7. The information handling system of claim 6 in response to sending the video information, the information handling system is operable to operate the video processor associated with the selected video output in a low power mode.

8. The information handling system of claim 1 wherein, in converting the first video signal into the second video signal, the video selector is further operable to convert a first frame rate associated with the first video signal into a second frame rate associated with the second video signal.

9. The information handling system of claim 8 wherein, in converting the first video signal into the second video signal, the video selector is further operable to apply a scalar factor to the first video signal to convert a first resolution of the first video signal into a second resolution of the second video signal.

10. The information handling system of claim 9 wherein the video selector is further operable to determine the second frame rate and the scalar factor in response to determining a device identifier associated with the first display.

11. The information handling system of claim 3 further comprising an allocator operatively coupled to the first video processor, the second video processor, and the video selector, wherein the allocator is operable to control the selector to couple the first video output to the selected one of the first or the second video inputs.

12. The information handling system of claim 11 wherein the allocator operates to control the video selector in response to an event at the information handling system.

13. A method comprising:

receiving a first video signal at a video selector from a first video processor associated with a first processing system, wherein the first video processor is operable to provide the first video signal in accordance with a first video format;

in response to receiving the first video signal, storing first video information based on the first video signal in a mid-stream frame buffer coupled to the video selector;

sending a second video signal from the video selector to a first display, wherein the first display is operable to receive the second video signal in accordance with a second video format, and wherein the second video format is different from the first video format;

sending a third video signal from the video selector to a second display, wherein the second display is operable to receive the third video signal in accordance with a third video format, and wherein the third video format is different from the first and second video formats;

in response to a first event, converting the first video signal into the second video signal in the video selector; and

in response to a second event, converting the first video signal into the third video signal in the video selector.

14. The method of claim 13 further comprising:

receiving a fourth video signal at the video selector from a second video processor associated with a second processing system, wherein the second video processor is operable to provide the fourth video signal in accordance with a fourth video format that is different from the first, second, and third video formats;

in response to receiving the fourth video signal, storing fourth video information based on the fourth video signal in the mid-stream frame buffer;

in response to a third event, converting the fourth video signal into the second video signal in the video selector; and

in response to a fourth event, converting the fourth video signal into the third video signal in the video selector.

15. The method of claim 14 further comprising:

prior to converting the first video signal into the second or third video signals, receiving at the video selector the first video signal from the mid-stream frame buffer; and

prior to converting the fourth video signal into the second or third video signals, receiving at the video selector the fourth video signal from the mid-stream frame buffer.

16. The method of claim 14 further comprising storing the second or third video signals in the mid-stream frame buffer.

17. A video selector comprising:

a memory interface operably coupleable to a mid-stream frame buffer;

a first receiver circuit having an input terminal operably coupleable to a first video output, and an output, and wherein the first receiver circuit is operable to;

receive a first video signal in accordance with a first video format; and

send the first video signal to the memory interface to store first video information based on the first video signal in the mid-stream frame buffer;

a second receiver circuit having an input terminal operably coupleable to a second video output, and an output, and wherein the second receiver circuit is operable to;

receive a second video signal in accordance with a second video format; and

send the second video signal to the memory interface to store second video information based on the second video signal in the mid-stream frame buffer;

a multiplexer having a first input coupled to the output of the first receiver circuit, a second input coupled to the output of the second receiver circuit, and an output, and operable to receive the first video signal and the second video signal from the memory interface; and

a converter having an input coupled to the output of the multiplexer, and an output, and wherein the converter is operable to provide a third video signal in accordance with a third video format;

wherein;

in response to the multiplexer coupling the output of the first receiver to the input of the converter, the converter operates to convert the first video signal into the third video signal; and

in response to the multiplexer coupling the output of the second receiver to the input of the converter, the converter operates to convert the second video signal into the third video signal.

18. The video selector of claim 17 further comprising:

a demultiplexer having an input coupled to the output of the converter, a first output terminal, and a second output terminal; and

wherein the video selector operates to provide the third video signal to a selected one of the first output terminal or the second output terminal.

19. The video selector of claim 18 wherein:

the first output terminal is operably coupleable to a first display device; and

the second output terminal is operably coupleable to a second display device.

20. The video selector of claim 17 wherein, in converting the first video signal into the third video signal, the converter is further operable to convert a first frame rate associated with the first video signal into a second frame rate associated with the third video signal.