PLASMA CVD APPARATUS, METHOD FOR FORMING MICROCRYSTALLINE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20110053357A1
• Filed: 08/20/2010
• Published: 03/03/2011
• Est. Priority Date: 08/25/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 9,177,761 B2
• Time in Patent Office: Days
• US Class Current: 438/488
• CPC Class Codes: C23C 16/45565 Shower nozzles
• CPC Class Codes: C23C 16/5096 Flat-bed apparatus
• CPC Class Codes: H01J 37/3244 Gas supply means
• CPC Class Codes: H01J 37/32449 Gas control, e.g. control of the gas flow
• CPC Class Codes: H01J 37/32541 Shape
• CPC Class Codes: H01J 37/32834 Exhausting
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A structure of a plasma CVD apparatus for forming a dense semiconductor film is provided. Further, a technique for forming a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains is provided. An electrode supplied with electric power for generating plasma is included in a reaction chamber of the plasma CVD apparatus. This electrode has a common plane on a surface opposite to a substrate, and the common plane is provided with depressed openings. Gas supply ports are provided on the bottom of the depressed openings or on the common plane of the electrode. The depressed openings are provided in isolation from one another.

Claims

1. A plasma CVD apparatus comprising,

a first electrode provided with a plurality of depressed openings on a common plane and supplied power;

and

a second electrode opposite to the common plane for placing a substrate,

wherein the common plane forms glow discharge plasma by being supplied the power,

wherein a gas supply port is provided for the plurality of depressed openings, and

wherein the plurality of depressed openings each have a tapered shape and are chamfered or roundly chamfered.

2. The plasma CVD apparatus according to claim 1, wherein the power supplied for the first electrode is high-frequency power.

3. The plasma CVD apparatus according to claim 1, wherein the power supplied for the first electrode is high-frequency power of 60 MHz or less.

4. The plasma CVD apparatus according to claim 1, wherein the glow discharge plasma has high electron density.

5. The plasma CVD apparatus according to claim 1, wherein a distance between the first electrode and the second electrode is greater than or equal to 4 mm and less than or equal to 16 mm.

6. The plasma CVD apparatus according to claim 1, wherein a heater is provided in the second electrode.

7. A plasma CVD apparatus comprising,

a first electrode provided with a plurality of depressed openings on a common plane and supplied power;

and

a second electrode opposite to the common plane for placing a substrate,

wherein the common plane forms glow discharge plasma by being supplied the power,

wherein a gas supply port provided for the common plane, and

wherein the plurality of depressed openings each have a tapered shape and are chamfered or roundly chamfered.

8. The plasma CVD apparatus according to claim 7, wherein the power supplied for the first electrode is high-frequency power.

9. The plasma CVD apparatus according to claim 7, wherein the power supplied for the first electrode is high-frequency power of 60 MHz or less.

10. The plasma CVD apparatus according to claim 7, wherein the glow discharge plasma has high electron density.

11. The plasma CVD apparatus according to claim 7, wherein a distance between the first electrode and the second electrode is greater than or equal to 4 mm and less than or equal to 16 mm.

12. The plasma CVD apparatus according to claim 7, wherein a heater is provided in the second electrode.

13. A method for manufacturing a microcrystalline semiconductor film comprising the steps of:

introducing a reactive gas into a reaction chamber through a gas supply port of a first electrode;

setting a pressure of the reaction chamber to greater than or equal to 450 Pa and less than or equal to 13332 Pa;

forming a plasma region between the first electrode and a second electrode by supplying power to the first electrode;

forming crystalline deposition precursors having crystallinity in a gas phase including the plasma region;

forming a crystal nucleus of greater than or equal to 5 nm and less than or equal to 15 nm by depositing the deposition precursors over a substrate; and

forming the microcrystalline semiconductor film by growing a crystal from the crystal nucleus,

wherein the first electrode has a common plane opposite to the second electrode and is provided with a plurality of depressed openings, and

wherein a distance between the first electrode and the second electrode is greater than or equal to 4 mm and less than or equal to 16 mm.

14. The method according to claim 13, wherein the power supplied for the first electrode is high-frequency power.

15. The method according to claim 13, wherein the power supplied for the first electrode is high-frequency power of 60 MHz or less.

16. The method according to claim 13, wherein the plasma region is high-density plasma region.

17. The method for manufacturing the microcrystalline semiconductor film according to claim 13, wherein a rare gas is included in the reactive gas.

18. The method for manufacturing the microcrystalline semiconductor film according to claim 13, wherein the gas supply port is provided on the plurality of depressed openings.

19. The method for manufacturing the microcrystalline semiconductor film according to claim 13, wherein the gas supply port is provided on the common plane.

20. A method for manufacturing a thin film transistor comprising the steps of:

forming a gate electrode over the substrate;

forming a gate insulating film which covers the gate electrode;

forming a microcrystalline semiconductor layer over the gate insulating film, using the method for manufacturing the microcrystalline semiconductor film according to claim 13; and

forming a wiring electrically connected to the microcrystalline semiconductor film.