REJECTION OF A CLOSE-IN-FREQUENCY INTERFERER EMPLOYING A LOG DETECTOR AND CLASSICAL DOWN CONVERTER

• US 20110053514A1
• Filed: 01/09/2009
• Published: 03/03/2011
• Est. Priority Date: 01/11/2008
• Status: Abandoned Application

• Current Assignee: Clemson University
• Original Assignee: Clemson University
• Inventors: Simoneau, Joel B., Pearson, J. Wilson
• Application Number:
  US12/811,877
• Publication Number:
  US 20110053514A1
• Time in Patent Office: Days
• US Class Current: 455/63.1
• CPC Class Codes: H03D 2200/0088 Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products
• CPC Class Codes: H03D 7/00 Transference of modulation from one carrier to another, e.g. frequency-changing H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference

Abstract

Disclosed is a methodology and apparatus for rejecting a high-power, near-in-frequency, radio frequency interference. The subject rejection methodology provides two branches; one is a classical down converter branch, and the other is a log detector followed by a high pass filter. The two branches produce a complex multiplication which cancels the highest inter modulation product and the final output is presented at the originally intended intermediate frequency. The methodology is appropriate for a constant-amplitude modulation on the interferer and any combination of phase, frequency, and amplitude modulation on the intended signal.

Claims

1. A method for rejecting interference between a desired signal and an interfering signal, comprising:

dividing an input signal into first and second portions;

providing first and second signal processing branches, each branch providing different signal processing methodologies;

applying a first portion of the divided input signal to the first processing branch;

applying a second portion of the divider input signal to the second processing branch;

combining the outputs of the first and second processing branches to produce a sum signal and a difference signal; and

selecting for further processing as an intermediate frequency signal one of the sum signal or the difference signal based on the sign of the difference between the frequency of a desired signal and the frequency of an interfering signal.

2. The method of claim 1, wherein the first branch comprises a down converter and the second branch comprises a logarithmic detector.

3. The method of claim 2, further comprising:

passing the signal from the first branch through a low-pass filter prior to combining the outputs; and

passing the signal from the second branch though a high-pass filter prior to combining the outputs.

4. The method of claim 3, further comprising:

separating each of the output signals from the first and second branches into in-phase and quadrature components; and

multiplying the in-phase components from each branch together;

multiplying the quadrature components from each branch together; and

combining the multiplied in-phase and quadrature components to produce the sum signal and difference signals.

5. Apparatus for rejecting interference between a desired signal and an interfering signal, comprising:

a divider having an input terminal and a pair of output terminals,

a first multiplier having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to one of the pair of output terminals from said divider;

a logarithmic detector having an input terminal and an output terminal, the input terminal coupled to another of the pair of output terminals from said divider; and

a hybrid device having first and second input terminals and first and second output terminals, the first output terminal configured to provide a signal corresponding to the sum of the signals applied to the first and second input terminals and the second output terminal configured to provide a signal corresponding to the difference between the signals applied to the first and second input terminals,

wherein the output terminal of the first multiplier is coupled to the first input of the hybrid device and the output terminal of the logarithmic detector is coupled to the second input of the hybrid device.

6. The apparatus of claim 5, further comprising:

a low-pass filter coupled between the output of the first multiplier and the first input of the hybrid device; and

a high-pass filter coupled between the output of the logarithmic detector and the second input of the hybrid device.

7. The apparatus of claim 6, further comprising:

an oscillator coupled to the second input of the first multiplier.

8. The apparatus of claim 7, further comprising:

a first 90°

hybrid divider having an input, an in-phase output, and a quadrature output;

a second 90°

hybrid divider having an input, an in-phase output, and a quadrature output;

a second multiplier having first and second inputs and an output; and

a third multiplier having first and second inputs and an output,

wherein the in-phase output of the first 90°

hybrid divider is coupled to the first input of the second multiplier, the quadrature output of the first 90°

hybrid divider is coupled to the second input of the third multiplier, the in-phase output of the second 90°

hybrid divider is coupled to the second input of the second multiplier, and the quadrature output of the second 90°

hybrid divider is coupled to the first input of the third multiplier.