Digital Signal Processing Systems

• US 20110055445A1
• Filed: 03/15/2010
• Published: 03/03/2011
• Est. Priority Date: 09/03/2009
• Status: Abandoned Application

• Current Assignee: Sunpower Corporation (Totalenergies Se)
• Original Assignee: Azuray Technologies, Inc
• Inventors: Batten, Robert, Slavin, Keith, DiTommaso, Vincenzo, Gee, Edward, Le, Triet Tu, Naiknaware, Ravindranath, Heiberg, Adam, Morel, Dennis
• Application Number:
  US12/724,376
• Publication Number:
  US 20110055445A1
• Time in Patent Office: Days
• US Class Current: 710/260
• CPC Class Codes: G06F 1/0353 by using symmetrical properties of the function, e.g. using most significant bits for quadrant control
• CPC Class Codes: G06F 2101/04 Trigonometric functions

Abstract

A signal processing system may include a multiply-accumulate (MAC) unit to generate output data by performing multiply-accumulate operations on first and second input data in response to a stream of MAC instruction words, where the MAC unit is pipelined to enable it to perform a multiply-accumulate operation in response to each MAC instruction word. The system may also include an instruction generator to generate the stream of MAC instruction words by performing loop expansion on a stream of intermediate instruction words, where one intermediate instruction word may comprise a group of fields to set up the MAC unit to execute in response to the one intermediate instruction word.

Claims

1. A signal processing system comprising:

a multiply-accumulate (MAC) unit to generate output data by performing multiply-accumulate operations on first and second input data in response to a stream of MAC instruction words, where the MAC unit is pipelined to enable it to perform a multiply-accumulate operation in response to each MAC instruction word; and

an instruction generator to generate the stream of MAC instruction words by performing loop expansion on a stream of intermediate instruction words;

where one intermediate instruction word may comprise a group of fields to set up the MAC unit to execute in response to the one intermediate instruction word.

2. The system of claim 1 where the group of fields to set up the MAC unit includes:

a field for the source of input data for the MAC unit;

a field for the source of coefficient data for the MAC unit;

a field for the destination of output data from the MAC unit; and

a field for a loop count.

3. The system of claim 2 where the group of fields to set up the MAC unit further includes:

a field to indicate a type of addressing for the source of input data for the MAC unit; and

a field to indicate buffer length for the source of input data for the MAC unit.

4. The system of claim 2 where the group of fields to set up the MAC unit further includes:

a field to indicate a type of addressing for the destination of output data from the MAC unit; and

a field to indicate buffer length for the destination of output data from the MAC unit.

5. The system of claim 2 where the group of fields to set up the MAC unit further includes a field to indicate a MAC operation as vector multiply without an accumulate operation.

6. The system of claim 1 further comprising:

a first memory to provide the first input data to the MAC unit; and

a second memory to provide the second input data to the MAC unit.

7. The system of claim 6 where:

the MAC unit may read or write the first memory during operation; and

the MAC unit may only read the second memory during operation.

8. The system of claim 3 further comprising a host processor to load the second memory while the MAC unit is not operating.

9. The system of claim 6 where the instruction generator includes a first-in first-out (FIFO) memory to buffer the stream of intermediate instruction words.

10. The system of claim 6 where the instruction generator includes loop expansion logic to perform the loop expansion.

11. The system of claim 10 where the loop expansion logic comprises a hardware counter.

12. The system of claim 6 where the instruction generator includes logic to switch the context of the MAC unit.

13. The system of claim 8 where each of the first and second memories include separate resources for multiple contexts.

14. The system of claim 8 where the instruction generator switches context between intermediate instruction words.

15. The system of claim 1 further comprising

a limit memory;

and

a limit circuit coupled to the MAC unit and the limit memory to compare the output data from the MAC unit to limit data stored in the limit memory.

16. The system of claim 15 where the limit circuit may limit the output data from the MAC unit based on the limit data stored in the limit memory.

17. The system of claim 15 where the limit circuit may assert a limit signal when output data from the MAC unit exceeds limit data stored in the limit memory.

18. The system of claim 17:

further comprising a supervisory processor; and

where the limit signal generates an interrupt for the supervisory processor.

19. The system of claim 17 where the limit signal is configured to disable a plant controlled by the signal processing system.

20. The system of claim 15 where the limit circuit compares the output data from the MAC unit to the limit data on a tick-by-tick basis.

21. The system of claim 15 where the limit memory includes resources for multiple contexts.

22. The system of claim 6 further comprising a multiplexer having a first input coupled to the first memory and an output coupled to the MAC unit to provide the first input data to the MAC unit.

23. The system of claim 22 where the multiplexer includes a second input to receive data from an input processing section.

24. The system of claim 6 further comprising logic to detect an approaching read-before-write condition.

25. The system of claim 24 further comprising logic to suspend the MAC unit in response to detecting the approaching read-before-write condition.

26. The system of claim 1 where the signal processing system comprises synchronous logic.

27. The system of claim 1 where the signal processing system comprises asynchronous logic.

33. The method of claim 25 where the number of threads is greater than the number of clock cycles between a read of the first memory used in a MAC unit instruction and a write of the MAC unit result.

28. A method comprising:

performing mutiply-accumulate operations on first and second input data in response to a stream of MAC instruction words, where a mutiply-accumulate operation is performed in response to each MAC instruction word; and

generating the stream of MAC instruction words by performing loop expansion on a stream of intermediate instruction words.

29. The method of claim 28 further comprising:

storing the first input data in a first memory; and

storing the second input data in a second memory.

30. The method of claim 29:

further comprising switching the context of the MAC unit between multiple threads in the streams of instructions;

where the first and second memories include separate resources for the multiple threads.

31. The method of claim 28 further comprising scheduling the threads to avoid read-before-write conditions.

32. The method of claim 29 where the multiple threads are scheduled in a circular manner.

34. The method of claim 28 further comprising:

detecting an approaching read-before-write condition; and

switching threads to avoid the read-before-write condition.

35. A method comprising:

processing a first stage of a decimation processes within a tick of a digital signal processing system; and

processing a second stage of the decimation process within the tick;

where the second stage is processed before the first stage within the tick.

36. The method of claim 35 further comprising processing a third stage of the decimating process within the tick, where the third stage is processed before the second stage within the tick.

37. The method of claim 35 further comprising performing a suspend operation after processing the first stage.

38. The method of claim 35 where the decimation process is a first decimation process, and the method further comprises:

processing a first stage of a second decimation processes within the tick; and

processing a second stage of the second decimation process within the tick;

where the second stage of the second decimation process is processed before the first stage of the second decimation process within the tick.

39. The method of claim 38 where:

each stage comprises a first routine and a second routine having a substantially longer execution time than the first routine; and

the stages are scheduled so that no more than one of the second routines are executed during the tick.

40. The method of claim 38 where:

the first stage of the first decimation process includes a first filter routine that generates first output data;

the second stage of the first decimation process includes a second filter routine that uses the first output data from the first filter routine; and

the first output data from the first filter routine is not returned to the second filter routine during a tick in which the first filter routine is executed.

41. The method of claim 38 where:

each first stage includes a filter routine, a data retrieval routine that uses data returned from a corresponding second stage, and a return instruction; and

the data retrieval routine is arranged between the filter routine and the return instruction in each first stage.

42. The method of claim 38 where:

the first decimation process comprises a first multi-stage FIR filter executed as a first thread; and

the second decimation process comprises a second multi-stage FIR filter executed as a second thread.

43. A method comprising:

compiling instructions for a digital signal processing system having multiple threads executed during ticks, where each tick includes a maximum predetermined number of instructions per thread, and each thread has a cycle length of a predetermined number of ticks; and

calculating the lowest common multiple of the cycle lengths of the threads.

44. The method of claim 43 further comprising analyzing the timing conditions for each tick for a number of combinations of threads determined by the lowest common multiple.

45. The method of claim 44 where analyzing the timing conditions for each tick comprises determining the number of instructions required for each tick for each of the number of combinations of threads determined by the lowest common multiple.

46. The method of claim 45 further comprising:

determining the maximum of the number of instructions required for each tick; and

comparing the maximum to the tick period to determine if the maximum of the number of instructions can be executed during a tick period.

47. The method of claim 46 further comprising issuing a warning if the maximum of the number of instructions exceeds the tick period.

48. The method of claim 46 further comprising changing the relative phases of the threads if the maximum of the number of instructions exceeds the tick period.

49. The method of claim 48 further comprising repeating analyzing the timing conditions for each tick for the number of combinations of threads determined by the lowest common multiple.

50. The method of claim 43 where calculating the lowest common multiple of the cycle lengths of the threads comprises:

calculating the product of the cycle lengths of the threads; and

dividing the product of the cycle lengths of the threads by the greatest common divisor of the cycle lengths of the threads.