Page based management of flash storage
First Claim
Patent Images
1. A data storage system comprising:
- an array of nonvolatile memory devices comprising multiple blocks of sub-arrays that are comprising a plurality of sub-blocks where each sub-block comprises a plurality of sectors and each sectors comprising a plurality of bytes of memory cells;
a management processor in communication with the array of nonvolatile memory devices to provide control signals for the programming of selected sub-blocks, erasing selected blocks, and reading selected sub-blocks of the array of nonvolatile memory devices;
a sub-block buffer in communication with the array of nonvolatile memory devices and the management processor and partitioned into sub-block segments for temporarily storing sub-blocks of data that is read from or to be transferred to the array of nonvolatile memory devices as determined by control signals received from the management processor; and
a logical-to-physical translation table that receives a requested logical sub-block address and translates the logical sub-block address to a physical sub-block address and in communication with the management processor to transfer the physical sub-block address to the management processor for identifying a physical location of a desired sub-block within the array of nonvolatile memory devices, wherein the logical-to-physical translation table comprises a cache flag table identifying if the requested logical sub-block address is present in the sub-block buffer.
2 Assignments
0 Petitions
Accused Products
Abstract
Methods and circuits for page based management of an array of Flash RAM nonvolatile memory devices provide paged base reading and writing and block erasure of a flash storage system. The memory management system includes a management processor, a page buffer, and a logical-to-physical translation table. The management processor is in communication with an array of nonvolatile memory devices within the flash storage system to provide control signals for the programming of selected pages, erasing selected blocks, and reading selected pages of the array of nonvolatile memory devices.
340 Citations
63 Claims
-
1. A data storage system comprising:
-
an array of nonvolatile memory devices comprising multiple blocks of sub-arrays that are comprising a plurality of sub-blocks where each sub-block comprises a plurality of sectors and each sectors comprising a plurality of bytes of memory cells; a management processor in communication with the array of nonvolatile memory devices to provide control signals for the programming of selected sub-blocks, erasing selected blocks, and reading selected sub-blocks of the array of nonvolatile memory devices; a sub-block buffer in communication with the array of nonvolatile memory devices and the management processor and partitioned into sub-block segments for temporarily storing sub-blocks of data that is read from or to be transferred to the array of nonvolatile memory devices as determined by control signals received from the management processor; and a logical-to-physical translation table that receives a requested logical sub-block address and translates the logical sub-block address to a physical sub-block address and in communication with the management processor to transfer the physical sub-block address to the management processor for identifying a physical location of a desired sub-block within the array of nonvolatile memory devices, wherein the logical-to-physical translation table comprises a cache flag table identifying if the requested logical sub-block address is present in the sub-block buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A memory management circuit for sub-blocked base reading and writing and block erasure of a flash storage system, wherein the memory management circuit comprises:
-
a management processor in communication with an array of nonvolatile memory devices within the flash storage system to provide control signals for the programming of selected sub-blocks, erasing selected blocks, and reading selected sub-blocks of the array of nonvolatile memory devices; a sub-block buffer in communication with the array of nonvolatile memory devices and the management processor and partitioned into sub-block segments for temporarily storing sub-blocks of data that are read from or to be transferred to the array of nonvolatile memory devices as determined by control signals received from the management processor; and a logical-to-physical translation table that receives a requested logical sub-block address and translates the logical sub-block address to a physical sub-block address and in communication with the management processor to transfer the physical sub-block address to the management processor for identifying a physical location of a desired sub-block within the array of nonvolatile memory devices, wherein the logical-to-physical translation table comprises a cache flag table identifying if the requested logical sub-block address is present in the sub-block buffer. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
-
-
30. A method for managing a flash storage system that is comprised of an array of nonvolatile memory devices, wherein the method for managing the flash storage system comprises the steps of:
-
reading or writing a sub-block from or to an array of nonvolatile memory devices within the flash storage system by the steps of; a) decoding a logical address of the sub-block, b) accessing the logical address in a logical-to-physical translation table to determine if the sub-block is resident in a sub-block buffer cache, c) if the sub-block is resident in the sub-block buffer cache, reading or writing the sub-block from or to the sub-block buffer cache, d) if the sub-block is not resident in the sub-block buffer cache, determining if the sub-block buffer cache has a free sub-block, e) if there is a free sub-block, assigning the logical address to be read or written to the free sub-block of the sub-block buffer cache, reading the sub-block from the array of nonvolatile devices to the assigned free sub-block and reading assigned free sub-block;
orwriting the sub-block to the assigned free sub-block, f) if there is not a free sub-block, evicting a least recently used sub-block from the sub-block buffer cache to create a free sub-block, and g) performing step e) to read or write the sub-block from or to the assigned free sub-block. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
-
-
44. A computer readable medium for retaining a computer program code which, when executed on a control processor, performs a computer program process for managing a flash storage, wherein the computer program process comprises the steps of:
reading or writing a sub-block from or to an array of nonvolatile memory devices within the flash storage system by the steps of; a) decoding a logical address of the sub-block, b) accessing the logical address in a logical-to-physical translation table to determine if the sub-block is resident in a sub-block buffer cache, c) if the sub-block is resident in the sub-block buffer cache, reading or writing the sub-block from or to the sub-block buffer cache, d) if the sub-block is not resident in the sub-block buffer cache, determining if the sub-block buffer cache has a free sub-block, e) if there is a free sub-block, assigning the logical address to be read or written to the free sub-block of the sub-block buffer cache, reading the sub-block from the array of nonvolatile devices to the assigned free sub-block and reading assigned free sub-block;
orwriting the sub-block to the assigned free sub-block, f) if there is not a free sub-block, evicting a least recently used sub-block from the sub-block buffer cache to create a free sub-block, and g) performing step e) to read or write the sub-block from or to the assigned free sub-block. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57)
-
58. A method for wearleveling an erased block of a flash storage system that is comprised of an array of nonvolatile memory devices divided into multiple blocks of sub-arrays, wherein the method for wearleveling comprises the steps of:
-
determining a sliding window erase count as a function of a lowest block erase count; determining if an erased block count of the erased block exceeds the sliding window erase count; if the sliding window erase count is exceeded, searching an erasure count table to determine a block having the lowest block erase count; selecting the block with the lowest block erase count; and copying all valid sub-blocks of the block with the lowest block erase count to the low order sub-blocks of the erased block; erasing the block with the lowest block erase count to become a newly erased block; incrementing the erasure count in the erasure count table for the newly erased block; and assigning the newly erase block as a new spare block available for writing. - View Dependent Claims (59, 60)
-
-
61. An apparatus for wearleveling an erased block of a flash storage system that is comprised of an array of nonvolatile memory devices divided into multiple blocks of sub-arrays, wherein the method for wearleveling comprises the steps of:
-
means for determining a sliding window erase count as a function of a lowest block erase count; means for determining if an erased block count of the erased block exceeds the sliding window erase count; means for searching an erasure count table to determine a block having the lowest block erase count, if the sliding window erase count is exceeded; means for selecting the block with the lowest block erase count; and means for copying all valid sub-blocks of the block with the lowest block erase count to the low order sub-blocks of the erased block; means for erasing the block with the lowest block erase count to become a newly erased block; means for incrementing the erasure count in the erasure count table for the newly erased block; and means for assigning the newly erase block as a new spare block available for writing. - View Dependent Claims (62, 63)
-
Specification