METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF

• US 20110055460A1
• Filed: 04/23/2010
• Published: 03/03/2011
• Est. Priority Date: 09/02/2009
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: LI, XIANGRONG, HU, SHUIHUA, Li, Wei-Qing, Chen, Bo
• Granted Patent: US 8,954,646 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies

Abstract

A method for managing a plurality of blocks of a Flash memory includes: recording/updating linking information regarding a logical block address, wherein the linking information includes a plurality of physical block addresses linking to the logical block address, and each physical block address represents a block of the plurality of blocks; and when a block represented by a physical block address of the plurality of physical block addresses has no any valid page, selectively erasing the block and removing the physical block address from the linking information. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks.

Claims

1. A method for managing a plurality of blocks of a Flash memory, the method comprising:

recording/updating linking information regarding a logical block address, wherein the linking information comprises a plurality of physical block addresses linking to the logical block address, and each physical block address represents a block of the plurality of blocks; and

when a block represented by a physical block address of the plurality of physical block addresses has no any valid page, selectively erasing the block and removing the physical block address from the linking information.

2. The method of claim 1, wherein the linking information further comprises current physical page location information, and the current physical page location information is utilized for indicating a location of a latest written physical page regarding the logical block address.

3. The method of claim 1, wherein the linking information further comprises page linking information;

and the method further comprises;

determining whether the block represented by the physical block address has no any valid page according to the page linking information.

4. The method of claim 3, wherein the page linking information comprises a logical-to-physical page linking table;

and the step of recording/updating the linking information regarding the logical block address further comprises;

in the logical-to-physical page linking table, regarding a logical page address belonging to the logical block address, recording/updating a corresponding physical block address or representative information thereof and further recording/updating a corresponding physical page address.

5. The method of claim 4, wherein the step of recording/updating the corresponding physical block address or the representative information thereof and further recording/updating the corresponding physical page address further comprises:

in the logical-to-physical page linking table, utilizing associated linking information of a physical block having a lower ranking regarding a physical block address table to update associated linking information of a physical block having a higher ranking regarding the physical block address table.

6. The method of claim 4, wherein the page linking information further comprises a pointer pointing to the logical-to-physical page linking table.

7. The method of claim 1, wherein the linking information further comprises a number of the physical block addresses.

8. The method of claim 1, wherein the step of selectively erasing the block and removing the physical block address from the linking information further comprises:

when the block represented by the physical block address has no any valid page, immediately erasing the block and removing the physical block address from the linking information.

9. The method of claim 1, wherein the step of selectively erasing the block and removing the physical block address from the linking information further comprises:

when the block represented by the physical block address has no any valid page, triggering an operation of erasing the block and removing the physical block address from the linking information based upon occurrence of a specific event.

10. The method of claim 1, wherein the step of selectively erasing the block and removing the physical block address from the linking information further comprises:

when a number of blocks that are within blocks represented by the physical block addresses and have no any valid page reaches a predetermined value, erasing all of the blocks that have no any valid page and removing physical block addresses thereof from the linking information.

11. The method of claim 1, wherein the step of selectively erasing the block and removing the physical block address from the linking information further comprises:

when a number of blocks represented by the physical block addresses reaches a predetermined value, merging valid pages of at least one portion of blocks within the blocks represented by the physical block addresses into at least one new blank block, and erasing the at least one portion of blocks and removing physical block addresses thereof from the linking information.

12. The method of claim 1, further comprising:

when physical pages of a specific block are continuously written in a same order of logical pages of a corresponding logical block, setting a pointer within linking information of the corresponding logical block to be null, in order to prevent the pointer from pointing to any logical-to-physical page linking table.

13. A memory device, comprising:

a Flash memory comprising a plurality of blocks; and

a controller arranged to access the Flash memory and manage the plurality of blocks, wherein the controller records/updates linking information regarding a logical block address, the linking information comprises a plurality of physical block addresses linking to the logical block address, and each physical block address represents a block of the plurality of blocks;

wherein when a block represented by a physical block address of the plurality of physical block addresses has no any valid page, the controller selectively erases the block and removes the physical block address from the linking information.

14. The memory device of claim 13, wherein the linking information further comprises current physical page location information, and the current physical page location information is utilized for indicating a location of a latest written physical page regarding the logical block address.

15. The memory device of claim 13, wherein the linking information further comprises page linking information;

and the controller determines whether the block represented by the physical block address has no any valid page according to the page linking information.

16. The memory device of claim 15, wherein the page linking information comprises a logical-to-physical page linking table;

and in the logical-to-physical page linking table, regarding a logical page address belonging to the logical block address, the controller records/updates a corresponding physical block address or representative information thereof and further records/updates a corresponding physical page address.

17. The memory device of claim 16, wherein in the logical-to-physical page linking table, the controller utilizes associated linking information of a physical block having a lower ranking regarding a physical block address table to update associated linking information of a physical block having a higher ranking regarding the physical block address table.

18. The memory device of claim 16, wherein the page linking information further comprises a pointer pointing to the logical-to-physical page linking table.

19. The memory device of claim 13, wherein the linking information further comprises a number of the physical block addresses.

20. The memory device of claim 13, wherein when the block represented by the physical block address has no any valid page, the controller immediately erases the block and removes the physical block address from the linking information.

21. The memory device of claim 13, wherein when the block represented by the physical block address has no any valid page, the controller triggers an operation of erasing the block and removing the physical block address from the linking information based upon occurrence of a specific event.

22. The memory device of claim 13, wherein when a number of blocks that are within blocks represented by the physical block addresses and have no any valid page reaches a predetermined value, the controller erases all of the blocks that no longer have no any valid page and removes physical block addresses thereof from the linking information.

23. The memory device of claim 13, wherein when a number of blocks represented by the physical block addresses reaches a predetermined value, the controller merges valid pages of at least one portion of blocks within the blocks represented by the physical block addresses into at least one new blank block, and erases the at least one portion of blocks and removes physical block addresses thereof from the linking information.

24. The memory device of claim 13, wherein when physical pages of a specific block are continuously written in a same order of logical pages of a corresponding logical block, the controller sets a pointer within linking information of the corresponding logical block to be null, in order to prevent the pointer from pointing to any logical-to-physical page linking table.

25. A controller of a memory device, the controller being utilized for accessing a Flash memory comprising a plurality of blocks, the controller comprising:

a read only memory (ROM) arranged to store a program code; and

a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks, wherein the controller that executes the program code by utilizing the microprocessor records/updates linking information regarding a logical block address, the linking information comprises a plurality of physical block addresses linking to the logical block address, and each physical block address represents a block of the plurality of blocks;

wherein when a block represented by a physical block address of the plurality of physical block addresses has no any valid page, the controller that executes the program code by utilizing the microprocessor selectively erases the block and removes the physical block address from the linking information.