METHOD FOR PRELOADING CONFIGURATIONS OF A RECONFIGURABLE HETEROGENEOUS SYSTEM FOR INFORMATION PROCESSING INTO A MEMORY HIERARCHY

• US 20110055480A1
• Filed: 02/06/2009
• Published: 03/03/2011
• Est. Priority Date: 02/08/2008
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Guyetant, Stéphane, Chevobbe, Stéphane
• Granted Patent: US 8,656,102 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

A method for preloading into a hierarchy of memories, bitstreams representing the configuration information for a reconfigurable processing system including several processing units. The method includes an off-execution step of determining tasks that can be executed on a processing unit subsequently to the execution of a given task. The method also includes, during execution of the given task, computing a priority for each of the tasks that can be executed. The priority depends on information relating to the current execution of the given task. The method also includes, during execution of the given task, sorting the tasks that can be executed in the order of their priorities. The method also includes, during execution of the given task, preloading into the memory, bitstreams representing the information of the configurations for the execution of the tasks that can be executed, while favoring the tasks whose priority is the highest.

Claims

1. A method for preloading into a hierarchy of memories bitstreams representing configuration information for a reconfigurable information processing system comprising a plurality of processing units of different types , the configuration describing a possible logical organization of the processing units which is suited to the execution of a given task, the method comprising:

determining off-execution tasks that can be executed on a processing unit of a given type subsequently to execution of the given task;

during execution of a given task, computing, for each of the tasks that can be executed, a priority dependent on information relating to the current execution of the given task;

during execution of the given task, sorting the tasks that can be executed in the order of their priorities; and

during execution of the given task, preloading into the hierarchy of memories, bitstreams representing the information of the configurations useful for the execution of the tasks that can be executed, while favoring the tasks whose priority is the highest.

2. The method as claimed in claim 1, wherein the preloading of the configurations is interrupted upon issuing by an operating system of a memory load request, said load request being processed first, so that the preloading does not slow down operation of the operating system.

3. The method as claimed in claim 1, wherein for each type of processing unit, constructing a dependency graph (TCDG) indicating the tasks that can be executed on the processing unit of the given type subsequently to execution of the given task.

4. The method as claimed in claim 3, wherein the dependency graph (TCDG) is constructed by using, for each task that can be executed on the processing unit of the given type subsequently to the execution of the given task, an application package process descriptive graph (CDG, CDFG).

5. The method as claimed in claim 1, wherein the priority of the task that can be executed is a weighted sum of N parameters p_i, i ε

{1, . . . ,N} where N is a nonzero integer, each parameter p_i in the sum being raised to a power n_i where n_i is a nonzero integer, parameters p_i being provided dynamically by an operating system during the execution.

6. The method as claimed in claim 5, wherein parameters p_i are provided statically before execution.

7. The method as claimed in claim 1, wherein the priority of the task that can be executed depends on process priorities provided by an operating system.

8. The method as claimed in claim 1, wherein the priority of the task that can be executed depends on a relative computational load of the processing units of the given type.

9. The method as claimed in claim 1, wherein the priority of the task that can be executed depends on a mean duration of execution on the processing units of the given type.

10. The method as claimed in claim 1, wherein the priority of the task that can be executed depends on probabilities of executing conditional instructions in the given task.

11. The method as claimed in claim 2, wherein the memory is a hierarchical memory.

12. The method as claimed in claim 1, wherein the configurations are preloaded into the hierarchy of memories as blocks of bits of parametrizable size.

13. The method as claimed in claim 1, wherein it is implemented in a hardware module, the reconfigurable system including a system on chip.

14. The method as claimed in claim 13, wherein the hardware module comprises a cache memory.