NON-INVASIVE TIMING CHARACTERIZATION OF INTEGRATED CIRCUITS USING SENSITIZABLE SIGNAL PATHS AND SPARSE EQUATIONS

• US 20110055781A1
• Filed: 08/28/2009
• Published: 03/03/2011
• Est. Priority Date: 08/28/2009
• Status: Active Grant

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Aristaeus Hermes LLC
• Inventors: Potkonjak, Miodrag
• Granted Patent: US 8,176,454 B2
• Time in Patent Office: Days
• US Class Current: 716/108
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Techniques for non-invasive, post-silicon characterization of signal propagation delay/timing of devices in an integrated circuit (IC) are generally disclosed. A system of equations may be developed based on a plurality of sensitizable signal paths (SSPs) of the IC for characterizing signal propagation delay or timing of devices within the SSPs. Input Vectors (IVs) may be selected and consecutively applied at one or more input sequential element devices of the IC associated with the SSPs with to produce corresponding output values at one or more output sequential element devices of the IC associated with the SSPs. Various pre-processing and post-processing techniques may be practiced to further improve accuracy of solution of the equations to enable efficient determination of solutions. Example techniques may include variable splitting, device clustering, IV and equation selection, and boosting, among others. Other aspects may also be disclosed and claimed.

Claims

1. A method for a computing device to characterize signal propagation delay associated with a plurality of devices in an integrated circuit (IC) having a plurality of sequential element devices, combinatorial devices and interconnects interconnecting the sequential element and combinatorial devices, the method for the computing device comprising:

receiving a specification that identifies the devices in the IC; and

forming a plurality of groupings of the devices using the specification, wherein each grouping of devices is associated with one of a plurality of sensitizable signal paths in the IC, wherein each sensitizable signal path comprises one or more interconnected sequential element devices;

forming one or more clusters of the devices to improve accuracy of solution of a set of equations associated with delays of the sensitizable signal paths;

receiving measurements of signal propagation delays responsive to two consecutive input vectors applied to the sequential elements associated with the plurality of sensitizable signal paths; and

solving the set of equations to determine the signal propagation delay characteristics of the plurality devices based at least in part on the received measurements.

2. The method of claim 1, wherein receiving measurements comprise receiving post-processed measurements processed to reduce measurement errors.

3. The method of claim 2, wherein processing of measurements comprises either performing statistical analysis of raw measurements, or boosting from raw measurements.

4. The method of claim 1, wherein forming a plurality of groupings of the devices associated with sensitizable paths comprises using transitive fan-ins of outputs of the combinatorial devices.

5. The method of claim 1, wherein forming one or more clusters of the devices comprises associating devices that are physically close to one another as one of the clusters.

6. The method of claim 1, wherein forming one or more clusters of devices comprises using a grid to partition the devices, wherein a distance of each device within a cluster to an intersection point of the grid is less than a predetermined threshold.

7. The method of claim 1, wherein solving the set of equations comprises using compressive sensing techniques.

8. The method of claim 1, wherein receiving a specification comprises receiving a specification expressed in a selected one of Hardware Description Language, Register Transfer Language or eXtensible Markup Language.

9. A method for characterizing timing associated with a plurality of devices in an integrated circuit (IC) having a plurality of sequential element devices, combinatorial devices and interconnects interconnecting the sequential element and combinatorial devices, the method comprising:

applying consecutively two input vectors to sequential element devices of the IC with a tester device, wherein the sequential element devices are associated with sensitizable signal paths in the IC, wherein the sensitizable signal paths are associated with a set of equations, with each of the sensitizable signal paths including one or more interconnected sequential element devices, and at least one of the sensitizable signal paths including a cluster of the devices that are clustered to increase accuracy of solution of the set of equations associated with the sensitizable signal paths;

measuring corresponding timing of responses of the sensitizable signal paths to the input vectors; and

determining the timing characteristics of the devices with a computing device by solving the set of equations using the measurements.

10. The method of claim 9, solving the set of equations comprises using compressive sensing techniques.

11. The method of claim 9, further comprising using a pre-processing technique to pre-process raw measurements to reduce measurement errors.

12. The method of claim 11, wherein using the pre-processing technique comprises one or more of selecting pairs of input vectors using backtracking such that the pairs of inputs allow an output of one or more sequential element devices to change, selecting the set of equations based on a number of variables in the set of equations, or selecting an input-output sequential element device pair, wherein the selected input-output sequential element device pair includes a selected one of the sequential element devices of the IC and another selected one of the sequential element devices of the IC with a substantially longest delay path between the selected sequential element devices.

13. An apparatus for characterizing signal propagation delay associated with a plurality of devices in an integrated circuit (IC) having a plurality of sequential element devices, combinatorial devices and interconnects interconnecting the sequential element and combinatorial devices, the apparatus comprising:

a processor; and

a computer-readable storage medium coupled to the processor and having stored therein a plurality of programming instructions configured to be executed by the processor, wherein when executed by the processor, cause the apparatus to;

receive a specification that identifies the devices in the IC;

form a plurality of groupings of the devices using the specification, wherein each grouping of devices is associated with one of a plurality of sensitizable signal paths in the IC associated with a set of equations, wherein each sensitizable signal path comprises one or more interconnected sequential element devices

form one or more clusters of the devices to increase accuracy of solution of the set of equations associated with the sensitizable signal paths;

receive measurements of signal propagation delays responsive to two consecutive inputs applied to the sequential element devices of the IC associated with the sensitizable signal paths; and

solve the set of equations to determine the signal propagation delay characteristics of the devices based at least in part on the received measurements.

14. The apparatus of claim 13, wherein the programming instructions are configured to cause the apparatus, when executed, to form the groupings of devices, using transitive fan-ins of one or more output terminals of the combinatorial devices

15. The apparatus of claims 13, wherein the programming instructions are configured to cause the apparatus, when executed, to associate combinatorial devices that are physically close to one another to form a cluster.

16. The apparatus of claim 13, wherein the programming instructions configured to cause the apparatus, when executed, to form the clusters of devices, are further configured to cause the apparatus to use a grid to partition the devices in the IC, wherein a distance of each device in a cluster to an intersection point of the grid is less than a predetermined threshold.

17. The apparatus of claim 13, wherein the programming instructions are further configured to cause the apparatus, when executed, to reduce the variables of the set of equations with a pre-processing technique.

18. The apparatus of claim 13, wherein the programming instructions are further configured to cause the apparatus, when executed, to perform processing on raw measurements to reduce measurement errors.

19. The apparatus of claim 18, wherein the programming instructions are further configured to cause the apparatus, when executed, to establish an interval of confidence to post-process the device characteristics.

20. An article of manufacture for characterizing timing associated with a plurality of devices in an integrated circuit (IC) having a plurality of sequential element devices, combinatorial devices and interconnects interconnecting the sequential element and combinatorial devices, the article of manufacture comprising:

a tangible computer-readable medium; and

a plurality of computer-executable instructions stored on the tangible computer-readable medium, wherein the computer-executable instructions, when executed by a processor of an apparatus, cause the apparatus to perform a method including;

applying consecutively two input vectors to sequential element devices associated with a plurality of sensitizable signal paths of the IC, using a tester device, wherein the sensitaizable signal paths are associated with a set of equations, and each of the sensitizable signal paths comprises interconnected sequential element devices with at least one of the sensitizable signal paths having a cluster of devices, wherein the devices are clustered to increase accuracy of solution of the set of equations associated with the sensitizable signal paths;

measuring timing of responses of the sensitizable signal paths; and

determining the timing characteristics of the devices by solving the set of equations using the measurements.

21. The article of manufacture of claim 20, wherein the method performed by the apparatus further comprises forming the one or more clusters of devices using multiple approximation grids.

22. The article of manufacture of claim 20, wherein the method performed by the apparatus further comprises selecting the set of equations to increase a number of variables that appear in another equal number of equations.

23. The article of manufacture of claim 20, wherein solving the equations comprise using compressive sensing techniques.

24. The article of manufacture of claim 20, wherein measuring timing of responses comprises measuring signal propagation time a plurality of times for statistical processing of variables in the set of equations.

25. The article of manufacture of claim 20, wherein the method performed by the apparatus further comprises selecting an input-output sequential element device pair, wherein the input-output sequential element device pair includes an input sequential element device of the IC and an output sequential element device of the IC with a number of variables less than a predetermined threshold.

26. The article of manufacture of claim 25, wherein the number of variables comprises a number of devices between the input and output sequential element devices.

27. A method for a computing device to characterize signal propagation delay associated with a plurality of devices in an integrated circuit (IC) having a plurality of sequential element devices, combinatorial devices and interconnects interconnecting the sequential element and combinatorial devices, the method for the computing device comprising:

forming a set of equations based on a plurality of sensitizable signal paths of the integrated circuit (IC) for modeling signal propagation delay of the devices in the integrated circuit, wherein the sensitizable signal paths comprise one or more interconnected sequential element devices, with at least one of the sensitizable signal path having a cluster of devices to improve accuracy of solution of the set of equations associated with the sensitizable signal paths;

applying a pre-processing technique to further improve accuracy of solution of the equations; and

selecting a plurality of input vectors (IVs) for applying to one or more input sequential element devices of the IC associated with the sensitizable signal paths to produce one or more outputs at one or more output sequential element devices of the IC, wherein the sequential element devices are associated with the sensitizable signal paths, which measurements are used to solve the equations to determine the timing characteristics of the devices.

28. The method of claim 27, wherein forming a set of equations comprises forming a set of equations based on a Hamming distance between the equations.

29. The method of claim 27, wherein applying a pre-processing technique comprises clustering devices of the IC based on physical proximity of the devices in the IC.

30. The method of claim 27, wherein applying a pre-processing technique comprises modifying the set of equations based on a number of variables in the set of equations.

31. The method of claim 27, further comprising post-processing one or more of delay characteristics of devices to improve accuracy.

32. The method of claim 31, wherein the post-processing comprises either applying a learn and test procedure to the one or more delay characteristic of devices based on a statistical model, or applying a boosting procedure to the one or more delay characteristics of devices.