CONFIGURABLE TELEVISION BROADCAST RECEIVING SYSTEM

• US 20110055888A1
• Filed: 08/31/2009
• Published: 03/03/2011
• Est. Priority Date: 08/31/2009
• Status: Abandoned Application

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Clardy, James, Dandekar, Shree A.
• Application Number:
  US12/550,472
• Publication Number:
  US 20110055888A1
• Time in Patent Office: Days
• US Class Current: 725/131
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/6112 involving terrestrial transmission, e.g. DVB-T
• CPC Class Codes: H04N 21/8166 involving executable data, e.g. software arrangements for executing specific programs G06F9/44; broadcasting computer programmes in broadcast systems H04H20/91; involving the movement of software or configuration parameters H04L67/34

Abstract

A configurable television broadcast receiving system includes an analog to digital converter that receives a broadcast television (TV) signal and converts it from an analog signal to a digital signal. A communication interface receives the digital signal and communicates it to a general purpose programmable processor. The processor processes the digital signal by performing arithmetic processes to the signal to create a processed signal. A display device is communicatively coupled to the processor, receives the processed signal and displays a video rendition according to the processed signal.

Claims

1. A device comprising:

an analog to digital converter receiving a broadcast television (TV) signal and converting it from an analog signal to a digital signal;

a general purpose programmable processor;

a communication interface receiving the digital signal and communicating it to the processor, wherein the processor processes the digital signal by performing arithmetic processes to the signal to create a processed signal; and

a display device communicatively coupled to the processor and receiving the processed signal and displaying a video rendition according to the processed signal.

2. The device of claim 1, wherein the processor processes the digital signal by demodulating the signal to extract a video portion.

3. The device of claim 1, wherein the processor performs more arithmetic operations than memory operations to the processed signal.

4. The device of claim 3, wherein the processor is a graphics processor.

5. The device of claim 4, wherein the processor is a three dimensional (3D) graphics processor.

6. The device of claim 1, wherein the processor performs one of identifying, demodulating, extracting video transport stream, decoding, de-interlacing, scaling, gamma correcting, contrast enhancing, frame rate correcting and high-definition up converting to the digital signal.

7. The device of claim 1, including an audio device providing an audio rendition according to the processed signal.

8. An information handling system (IHS) comprising:

a central processing unit (CPU);

a memory coupled to the CPU; and

a television (TV) receiver system coupled to the CPU, wherein the TV receiver system includes;

an analog to digital converter receiving a broadcast television (TV) signal and converting it from an analog signal to a digital signal;

a general purpose programmable processor;

a communication interface receiving the digital signal and communicating it to the processor, wherein the processor processes the digital signal by performing arithmetic processes to the signal to create a processed signal; and

a display device communicatively coupled to the processor and receiving the processed signal and displaying a video rendition according to the processed signal.

9. The IHS of claim 8, wherein the processor processes the digital signal by demodulating the signal to extract a video portion.

10. The IHS of claim 8, wherein the processor performs more arithmetic operations than memory operations to the processed signal.

11. The IHS of claim 10, wherein the processor is a graphics processor.

12. The IHS of claim 11, wherein the processor is a three dimensional (3D) graphics processor.

13. The IHS of claim 8, wherein the processor performs one of identifying, demodulating, extracting video transport stream, decoding, de-interlacing, scaling, gamma correcting, contrast enhancing, frame rate correcting and high-definition up converting to the digital signal.

14. The IHS of claim 8, including an audio device providing an audio rendition according to the processed signal.

15. A method comprising:

receiving a broadcast television (TV) signal;

converting the TV signal from an analog signal to a digital signal;

processing the digital signal using a general purpose programmable processor, wherein the general purpose programmable processor is performing arithmetic processes to the signal to create a processed signal; and

displaying a video rendition according to the processed signal.

16. The method of claim 15, including processing the digital signal by demodulating the digital signal to extract a video portion.

17. The method of claim 15, wherein the processor is performing more arithmetic operations than memory operations to the processed signal.

18. The method of claim 17, using a graphics processor as the general purpose programmable processor.

19. The method of claim 15, including performing one of identifying, demodulating, extracting video transport stream, decoding, de-interlacing, scaling, gamma correcting, contrast enhancing, frame rate correcting and high-definition up converting to the digital signal.

20. The method of claim 15, including providing an audio rendition according to the processed signal to an audio device.