SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20110057188A1
• Filed: 08/31/2010
• Published: 03/10/2011
• Est. Priority Date: 09/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Maruyama, Hotaka, Oikawa, Yoshiaki, Noda, Kosei, Sakakura, Masayuki, Sakata, Junichiro, Yamazaki, Shunpei
• Granted Patent: US 8,541,780 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

It is an object to manufacture a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. An insulating layer which covers an oxide semiconductor layer of the thin film transistor contains a boron element or an aluminum element. The insulating layer containing a boron element or an aluminum element is formed by a sputtering method using a silicon target or a silicon oxide target containing a boron element or an aluminum element. Alternatively, an insulating layer containing an antimony (Sb) element or a phosphorus (P) element instead of a boron element covers the oxide semiconductor layer of the thin film transistor.

Claims

1. A semiconductor device comprising:

a first insulating layer over a substrate;

an oxide semiconductor layer over the first insulating layer; and

a second insulating layer over the oxide semiconductor layer,

wherein the first insulating layer and the second insulating layer each contain a boron element or an aluminum element at greater than or equal to 1×

10¹⁸ cm<sup>−

3</sup> and less than or equal to 1×

10²² cm<sup>−

3</sup>.

2. The semiconductor device according to claim 1, wherein the second insulating layer is in contact with the oxide semiconductor layer

3. The semiconductor device according to claim 1, further comprising a third insulating layer formed of silicon oxide between the second insulating layer and the oxide semiconductor layer,

wherein the third insulating layer does not contain a boron element, an aluminum element, a phosphorus element, or an antimony element.

4. The semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are each formed of silicon oxide.

5. A semiconductor device comprising:

a first insulating layer over a substrate;

an oxide semiconductor layer over the first insulating layer; and

a second insulating layer over the oxide semiconductor layer,

wherein the first insulating layer and the second insulating layer each contain a phosphorus element or an antimony element at greater than or equal to 1×

10¹⁹ cm <sup>−

3</sup> and less than or equal to 3×

10²¹ cm<sup>−

3</sup>.

6. The semiconductor device according to claim 5, wherein the second insulating layer is in contact with the oxide semiconductor layer.

7. The semiconductor device according to claim 5, further comprising a third insulating layer formed of silicon oxide between the second insulating layer and the oxide semiconductor layer,

wherein the third insulating layer does not contain a boron element, an aluminum element, a phosphorus element, or an antimony element.

8. The semiconductor device according to claim 5, wherein the first insulating layer and the second insulating layer are each formed of silicon oxide.

9. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate;

forming an oxide semiconductor layer over the gate electrode layer;

subjecting the oxide semiconductor layer to dehydration or dehydrogenation, wherein water or hydrogen is prevented from entering the oxide semiconductor layer without exposure to air after the dehydration or the dehydrogenation;

subjecting the oxide semiconductor layer to plasma treatment using N₂O, N₂, or Ar; and

forming an insulating layer in contact with at least a part of the oxide semiconductor layer after the plasma treatment.

10. The method for manufacturing a semiconductor device, according to claim 9, further comprising the step of forming a second insulating layer containing a boron element, an aluminum element, a phosphorus element, or an antimony element over the insulating layer by a sputtering method.

11. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate;

forming a first insulating layer over the gate electrode layer by a sputtering method;

forming an oxide semiconductor layer over the first insulating layer;

subjecting the oxide semiconductor layer to dehydration or dehydrogenation, wherein water or hydrogen is prevented from entering the oxide semiconductor layer without exposure to air after the dehydration or the dehydrogenation;

subjecting the oxide semiconductor layer to plasma treatment using N₂O, N₂, or Ar; and

forming a second insulating layer over the oxide semiconductor layer by a sputtering method,

wherein the first insulating layer and the second insulating layer are each formed by a sputtering method using a silicon target and each contain a boron element, an aluminum element, a phosphorus element, or an antimony element.

12. The method for manufacturing a semiconductor device, according to claim 11, further comprising the step of forming a third insulating layer in contact with at least a part of the oxide semiconductor layer after the plasma treatment,

wherein the third insulating layer is formed of silicon oxide by a sputtering method using a silicon target.