FLAT-PANEL DISPLAY SEMICONDUCTOR PROCESS FOR EFFICIENT MANUFACTURING

• US 20110057193A1
• Filed: 11/15/2010
• Published: 03/10/2011
• Est. Priority Date: 12/09/2008
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Lu, Jeng Ping, Ho, Jackson H.
• Granted Patent: US 8,174,078 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.

Claims

1-18. -18. (canceled)

19. A structure comprising:

a substrate;

a bottom gate deposited on the substrate;

a dielectric layer deposited on the bottom gate;

doped source and drain regions deposited on the substrate and formed around the bottom gate; and

a channel silicon precursor layer deposited on the patterned doped amorphous silicon layer and the dielectric layer.

20. The structure of claim 19 wherein the substrate is a glass substrate, a flexible metal, or a plastic substrate.

21. The structure of claim 19 wherein the doped amorphous silicon layer has a low concentration of hydrogen atoms.

22. The structure of claim 19 further comprising a passivation layer on the channel silicon precursor layer.

23. A display panel comprising:

a substrate; and

a thin film transistor (TFT) array having a plurality of TFTs as pixel switching devices on the substrate, each of the TFTs having a bottom gate structure with polycrystalline silicon and data interconnecting lines, the bottom gate structure and the data interconnecting lines being under a silicon layer.

24. The display panel of claim 23 further comprising:

a peripheral driver circuit coupled to the TFT array to drive the pixel switching devices, the peripheral driver circuit having a poly-last architecture.

25. The display panel of claim 23 wherein the substrate is a glass substrate, a flexible metal, or a plastic substrate.

26. The display panel of claim 23 wherein the bottom gate structure comprises:

a bottom gate deposited on the substrate;

a dielectric layer deposited on the bottom gate;

doped source and drain regions deposited on the substrate and formed around the bottom gate; and

a channel silicon precursor layer deposited on the patterned doped amorphous silicon layer and the dielectric layer.

27. The display panel of claim 26 wherein the doped amorphous silicon layer has a low concentration of hydrogen atoms.

28. The display panel of claim 26 wherein the bottom gate structure further comprises a passivation layer on the channel silicon precursor layer