SEMICONDUCTOR DEVICES AND METHODS OF FORMING THEREOF

• US 20110057237A1
• Filed: 09/01/2010
• Published: 03/10/2011
• Est. Priority Date: 09/04/2009
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Lim, Jong-Won, Chang, Woojin, AHN, Hokyun, Kim, Hae Cheon, Yoon, Hyung Sup
• Granted Patent: US 8,518,794 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66863 Lateral single gate transistors
• CPC Class Codes: H01L 29/8128 with recessed gate

Abstract

Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.

Claims

1. A semiconductor device comprising:

a substrate;

an active layer on the substrate;

a capping layer on the active layer;

source/drain electrodes on the capping layer;

a gate electrode on the active layer; and

a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.

2. The semiconductor device of claim 1, wherein the first void region and the second void region have different forms.

3. The semiconductor device of claim 1, further comprising a first insulation layer on the capping layer,

wherein the first void region includes a first void upper region on the first insulation layer and a first void lower region below the first insulation layer.

4. The semiconductor device of claim 3, wherein the gate electrode comprises a gate foot contacting the active layer and a gate head on the gate foot, and a width of the gate head is broader than a width of the gate foot.

5. The semiconductor device of claim 4, further comprising:

a second insulation layer on the first insulation layer; and

a third insulation layer spaced apart from the first insulation layer, with the second insulation layer therebetween,

wherein the second insulation layer has an etch selectivity with respect to the first and third insulation layers.

6. The semiconductor device of claim 5, wherein the gate head is disposed on the third insulation layer.

7. The semiconductor device of claim 5, wherein the gate foot is spaced apart from the second insulation layer and the capping layer.

8. The semiconductor device of claim 5, wherein the first void lower region is defined by a space between a first sidewall of the gate foot and the capping layer and a space between the first insulation layer and the active layer.

9. The semiconductor device of claim 8, wherein the first void upper region is defined by a space between the first sidewall of the gate foot and the second insulation layer and a space between the first insulation layer and the third insulation layer.

10. The semiconductor device of claim 9, wherein the second void region is disposed on a second sidewall of the gate foot and is defined by a space between the third insulation layer and the active layer.

11. The semiconductor device of claim 10, wherein the source/drain electrodes include a source electrode and a drain electrode, and a distance between the gate foot and the source electrode is shorter than that between the gate foot and the drain electrode.

12. The semiconductor device of claim 11, wherein a distance between the first sidewall of the gate foot and the capping layer is shorter than that between the second sidewall of the gate foot and the capping layer.

13. A method of forming a semiconductor device, the method comprising:

preparing a substrate;

sequentially forming an active layer and a capping layer on the substrate;

forming source/drain electrodes on the capping layer;

forming a first insulation layer on the source/drain electrodes;

exposing the capping layer by etching a portion of the first insulation layer;

sequentially forming a second and a third insulation layers on the capping layer and the first insulation layer;

forming an opening exposing a portion of the second insulation layer by etching a portion of the third insulation layer;

forming a first recess exposing the capping layer by etching the second insulation layer through the opening;

forming a second recess exposing the active layer by etching the capping layer; and

forming in the opening a gate electrode connected to the active layer.

14. The method of claim 13, wherein the second insulation layer has an etch selectivity with respect to the first and third insulation layers.

15. The method of claim 14, wherein the etching of the portion of the third insulation layer is performed using an anisotropic etching process.

16. The method of claim 15, wherein the anisotropic etching process uses an etching recipe having a higher etching rate with respect to the third insulation layer than the second insulation layer.

17. The method of claim 14, wherein the exposing of the capping layer by etching the second insulation layer through the opening is performed using an isotropic etching process.

18. The method of claim 17, wherein the isotropic etching process uses an etching recipe having a higher etching rate with respect to the second insulation layer than the first and third insulation layers.

19. The method of claim 13, wherein a width of the first recess is broader than that of the opening.

20. The method of claim 13, wherein a width of the second recess is broader than that of the opening.