VARIED SILICON RICHNESS SILICON NITRIDE FORMATION

• US 20110057248A1
• Filed: 09/09/2009
• Published: 03/10/2011
• Est. Priority Date: 09/09/2009
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: MA, Yi, OGLE, Robert, FANG, Shenqing
• Granted Patent: US 9,012,333 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.

Claims

1. A method comprising:

forming a tunnel oxide layer on a substrate;

depositing via atomic layer deposition a first layer of silicon nitride over said tunnel oxide layer, said first layer of silicon nitride comprises a first silicon richness; and

depositing via atomic layer deposition a second layer of silicon nitride over said first layer of silicon nitride, said second layer of silicon nitride comprises a second silicon richness that is different than said first silicon richness.

2. The method of claim 1, wherein said second silicon richness is less than said first silicon richness.

3. The method of claim 1, wherein said second silicon richness is greater than said first silicon richness.

4. The method of claim 1, wherein said first layer of silicon nitride comprises a stoichiometric silicon nitride film.

5. The method of claim 4, wherein said second layer of silicon nitride comprises a stoichiometric silicon nitride film.

6. The method of claim 1, wherein said second layer of silicon nitride comprises a stoichiometric silicon nitride film.

7. The method of claim 1, wherein said first layer of silicon nitride and said second layer of silicon nitride are part of a non-volatile memory.

8. The method of claim 1, wherein said substrate comprises silicon.

9. An integrated circuit memory device comprising:

a substrate;

a tunnel oxide layer disposed over said substrate;

a first layer of silicon nitride disposed over said tunnel oxide layer via atomic layer deposition, said first layer of silicon nitride comprises a first silicon richness; and

a second layer of silicon nitride disposed over said first layer of silicon nitride via atomic layer deposition, said second layer of silicon nitride comprises a second silicon richness that is different than said first silicon richness.

10. The integrated circuit memory device of claim 9, wherein said second silicon richness is less than said first silicon richness.

11. The integrated circuit memory device of claim 9, wherein said second silicon richness is greater than said first silicon richness.

12. The integrated circuit memory device of claim 9, wherein said substrate comprises silicon.

13. The integrated circuit memory device of claim 9, further comprising:

a third layer of silicon nitride disposed over said second layer of silicon nitride via atomic layer deposition, said third layer of silicon nitride comprises a third silicon richness that is different than said second silicon richness.

14. The integrated circuit memory device of claim 13, wherein said third silicon richness is less than said second silicon richness.

15. The integrated circuit memory device of claim 13, wherein said third silicon richness is greater than said second silicon richness.

16. The integrated circuit memory device of claim 13, wherein said third layer of silicon nitride comprises a stoichiometric silicon nitride film.

17. A method comprising:

forming a tunnel oxide layer on a silicon substrate;

depositing via atomic layer deposition a first layer of silicon nitride over said tunnel oxide layer, said first layer of silicon nitride comprising a first silicon richness; and

depositing via atomic layer deposition a second layer of silicon nitride over said first layer of silicon nitride, said second layer of silicon nitride comprising a second silicon richness that is less than said first silicon richness.

18. The method of claim 17, further comprising:

depositing via atomic layer deposition a third layer of silicon nitride over said second layer of silicon nitride, said third layer of silicon nitride comprising a third silicon richness that is less than said second silicon richness.

19. The method of claim 18, wherein said third layer of silicon nitride comprises a stoichiometric silicon nitride film.

20. The method of claim 17, wherein said first layer of silicon nitride and said second layer of silicon nitride are part of an integrated circuit non-volatile memory.