METHOD FOR FORMING A THICK BOTTOM OXIDE (TBO) IN A TRENCH MOSFET

• US 20110057259A1
• Filed: 09/04/2009
• Published: 03/10/2011
• Est. Priority Date: 09/04/2009
• Status: Abandoned Application

• Current Assignee: Monolithic Power Systems Incorporated
• Original Assignee: Monolithic Power Systems Incorporated
• Inventors: Li, Tiesheng
• Application Number:
  US12/554,326
• Publication Number:
  US 20110057259A1
• Time in Patent Office: Days
• US Class Current: 257/333
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a thick bottom oxide in the bottom of a trench used in a vertical MOSFET. Initially, an n-type substrate has an n-type epitaxial layer grown thereon. A top portion of the n-type epitaxial layer is implanted with p-type dopants to provide a p-layer. A trench is then etched into the p- and n-type epitaxial layer. A high density plasma chemical vapor deposition (HDPCVD) process is used to either partially or fully fill the trench. Any oxide on the top surface of the p-layer is then removed, such as by using a chemical mechanical polishing step. Then, an isotropic etching step, such as a wet etch, is used to remove the silicon dioxide from the trench, while leaving a thick bottom oxide at the bottom of the trench. The HDPCVD process utilizes minimal thermal budget to form the thick bottom oxide.

Claims

1. A method for forming a thick bottom oxide for a trench MOSFET comprising:

forming a trench in a semiconductor substrate;

using a high density plasma chemical vapor deposition (HDPCVD) process to form silicon dioxide at least partially into the trench and on a top surface of said substrate;

removing the silicon dioxide from the top surface of the substrate; and

removing the silicon dioxide from the sidewalls of the trench.

2. The method of claim 1 wherein the removing the silicon dioxide from the sidewalls of the trench is performed during the removing the silicon dioxide form the top surface of the substrate.

3. The method of claim 1 wherein the removing of the silicon dioxide from the top surface of the substrate is by a chemical mechanical polishing process.

4. The method of claim 1 wherein the silicon substrate is an n-type epitaxial layer formed atop of an n-type substrate, and further wherein said n-type epitaxial layer has a p-type implant formed therein.

5. The method of claim 1 wherein the silicon dioxide fills the trench.

6. The method of claim 3 further wherein a nitride layer is formed prior to the HDPCVD process and the nitride layer is used as a stop layer for the chemical mechanical polishing.

7. The method of claim 1 further including forming a gate oxide on the sidewalls of the trench by using a thermal oxidation process.

8. The method of claim 1 wherein the HDPCVD process occurs at a temperature of under 300 degrees Celsius.

9. The method of claim 1 wherein the process of removing the silicon dioxide on the sidewalls of the trench is by an isotropic wet etch process.

10. A MOSFET trench with a thick bottom oxide comprising:

a trench in a semiconductor substrate; and

a thick bottom oxide formed in the bottom of the trench, the thick bottom oxided formed by;

using a high density plasma chemical vapor deposition (HDPCVD) process to form silicon dioxide at least partially into the trench and on a top surface of said substrate;

removing the silicon dioxide from the top surface of the substrate; and

removing the silicon dioxide from the sidewalls of the trench.

11. The MOSFET trench of claim 10 wherein the removing the silicon dioxide from the sidewalls of the trench is performed during the removing the silicon dioxide form the top surface of the substrate.

12. The MOSFET trench of claim 10 wherein the removing of the silicon dioxide from the top surface of the substrate is by a chemical mechanical polishing process.

13. The MOSFET trench of claim 10 wherein the silicon substrate is an n-type epitaxial layer formed atop of an n-type substrate, and further wherein said n-type epitaxial layer has a p-type implant formed therein.

14. The MOSFET trench of claim 10 wherein the silicon dioxide fills the trench.

15. The MOSFET trench of claim 12 further wherein a nitride layer is formed prior to the HDPCVD process and the nitride layer is used as a stop layer for the chemical mechanical polishing.

16. The MOSFET trench of claim 10 further including forming a gate oxide on the sidewalls of the trench by using a thermal oxidation process.

17. The MOSFET trench of claim 10 wherein the HDPCVD process occurs at a temperature of under 300 degrees Celsius.

18. The MOSFET trench of claim 10 wherein the process of removing the silicon dioxide on the sidewalls of the trench is by an isotropic wet etch process.

19. A method for forming a thick bottom oxide for a trench MOSFET comprising:

forming an epitaxial layer atop of a semiconductor substrate, the epitaxial layer of same conductive type as the semiconductor substrate;

forming a hard mask over said epitaxial layer and patterning said hard mask to define a trench area;

forming a trench in said epitaxial layer by selectively etching said epitaxial layer and using said hard mask;

using a high density plasma chemical vapor deposition (HDPCVD) process to form silicon dioxide at least partially into the trench and on a top surface of said hard mask;

removing the silicon dioxide from the surface of the hard mask; and

removing the silicon dioxide from the sidewalls of the trench.

20. The method of claim 19 wherein the removing the silicon dioxide from the sidewalls of the trench is performed during the removing the silicon dioxide form the top surface of the hard mask.

21. The method of claim 19 wherein the removing of the silicon dioxide from the top surface of the hard mask is by a chemical mechanical polishing process.

22. The method of claim 19 wherein the substrate is n-type and said epitaxial layer is also n-type.

23. The method of claim 22 wherein an implantation process is used to form a p-layer in said n-type epitaxial layer.

24. The method of claim 19 further including forming a gate oxide on the sidewalls of the trench by using a thermal oxidation process.

25. A method for forming a thick bottom oxide for a trench MOSFET comprising:

forming an epitaxial layer atop of a semiconductor substrate, the epitaxial layer of same conductive type as the semiconductor substrate;

forming a hard mask over said epitaxial layer and patterning said hard mask to define a trench area;

forming a trench in said epitaxial layer by selectively etching said epitaxial layer and using said hard mask;

using a high density plasma chemical vapor deposition (HDPCVD) process to form silicon dioxide at least partially into the trench and on a top surface of said hard mask;

removing the silicon dioxide from the sidewalls of the trench;

forming a gate oxide on the sidewalls of the trench using thermal oxidation;

depositing a polysilicon layer until the trench is substantially filled;

performing a chemical mechanical polish until the polysilicon and silicon dioxide is removed from atop the hard mask; and

using implantation to implant the epitaxial layer until a top portion of the epitaxial layer is of opposite conductivity than the epitaxial layer.

26. The method of claim 25 wherein the substrate is n-type and said epitaxial layer is also n-type.