SEMICONDUCTOR DEVICE

• US 20110057262A1
• Filed: 09/10/2009
• Published: 03/10/2011
• Est. Priority Date: 09/10/2009
• Status: Active Grant

• Current Assignee: Episil Technologies Incorporated
• Original Assignee: Episil Technologies Incorporated
• Inventors: Ma, Shih-Kuei, Kuo, Ta-Chuan
• Granted Patent: US 8,237,223 B2
• Time in Patent Office: Days
• US Class Current: 257/337
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device including a substrate, an epitaxial layer, a first sinker, a transistor, a diode unit, a first buried layer, and a second buried layer is provided. When the semiconductor device is operated at the high voltage, the highly large substrate current due to the external load is avoided through the diode unit disposed in the semiconductor device of an embodiment consistent with the invention. Furthermore, according to the design of the semiconductor device, the issue of the narrow input voltage range is improved, and interference of the semiconductor device with the other semiconductor devices is prevented.

Claims

1. A semiconductor device comprising:

a substrate having a first conductivity type;

an epitaxial layer having a second conductivity type and disposed on the substrate;

a first sinker having the second conductivity type, disposed in the epitaxial layer, extending from the substrate to an upper surface of the epitaxial layer, and partitioning the epitaxial layer into a first region and a second region;

a transistor disposed in the first region, wherein a drain of the transistor is electrically coupled to a first rail, and a source of the transistor is electrically coupled to a second rail; and

a diode unit disposed in the second region and electrically coupled to the first rail.

2. The semiconductor device as claimed in claim 1, further comprising:

a first buried layer having the first conductivity type and disposed between the first region and the substrate; and

a second buried layer having the second conductivity type and disposed between the first buried layer and the substrate and between the second region and the substrate, wherein the second buried layer disposed between the first buried layer and the substrate is connected with the first sinker.

3. The semiconductor device as claimed in claim 1, wherein the diode unit is further electrically coupled to the first sinker.

4. The semiconductor device as claimed in claim 1, wherein the diode unit comprising:

a doped region having the first conductivity type, disposed in the epitaxial layer, and electrically coupled to the first rail; and

a second sinker having the second conductivity type and extending from the substrate to the upper surface of the epitaxial layer,

wherein the second buried layer disposed between the second region and the substrate is connected with the second sinker, and the diode unit is electrically coupled to the first sinker through the second sinker.

5. The semiconductor device as claimed in claim 1, wherein the first rail is electrically coupled to a system power, and the second rail is electrically coupled to an output pad.

6. The semiconductor device as claimed in claim 1, wherein the first rail is electrically coupled to an output pad, and the second rail is grounded.

7. The semiconductor device as claimed in claim 1, further comprising a third buried layer having the first conductivity type, wherein the third buried layer is disposed below the first buried layer and between the second buried layer and the substrate.

8. The semiconductor device as claimed in claim 1, wherein a doping concentration of the third buried layer is greater than that of the substrate.

9. The semiconductor device as claimed in claim 1, wherein a doping concentration of the first buried layer is greater than that of the substrate.

10. The semiconductor device as claimed in claim 1, wherein the transistor is a high voltage metal-oxide-semiconductor field effect transistor.

11. The semiconductor device as claimed in claim 1, wherein the first conductivity type is P-type, and the second conductivity type is N-type.

12. The semiconductor device as claimed in claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type.