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ARRANGING THROUGH SILICON VIAS IN IC LAYOUT

  • US 20110057319A1
  • Filed: 09/09/2009
  • Published: 03/10/2011
  • Est. Priority Date: 09/09/2009
  • Status: Active Grant
First Claim
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1. A method comprising:

  • identifying linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs; and

    modifying at least the portion of the IC layout to reduce a number of the linearly aligned TSVs.

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