ARRANGING THROUGH SILICON VIAS IN IC LAYOUT

• US 20110057319A1
• Filed: 09/09/2009
• Published: 03/10/2011
• Est. Priority Date: 09/09/2009
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Lindgren, Peter J., Dean, Donald R. JR., Stamper, Anthony K., Sprogis, Edmund J., Miles, Glen L.
• Granted Patent: US 8,136,084 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate

Abstract

A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.

Claims

1. A method comprising:

identifying linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs; and

modifying at least the portion of the IC layout to reduce a number of the linearly aligned TSVs.

2. The method of claim 1, wherein the portion includes an array of substantially uniform periodicity of through silicon via (TSV) sets, each of the TSV sets being arranged in a given direction, and the identifying includes:

defining a TSV set evaluation rectangle about each TSV set, each TSV set evaluation rectangle having a pair of X edges and a pair of Y edges,

calculating a Y spacing between adjacent TSV evaluation rectangles and an X spacing between adjacent TSV evaluation rectangles, and

expanding each TSV evaluation rectangle edge, excepting at a chip edge, in at least one Y direction by half the Y spacing between adjacent TSV evaluation rectangles and in at least one X direction by half the X spacing between adjacent TSV evaluation rectangles; and

the modifying includes;

in response to a Y edge of a selected, expanded TSV evaluation rectangle contacting a Y edge of an adjacent, expanded TSV evaluation rectangle or an X edge of the selected, expanded TSV evaluation rectangle contacting an X edge of an adjacent, expanded TSV evaluation rectangle, rotating the TSV set within the selected TSV evaluation rectangle to be non-aligned to the given direction.

3. The method of claim 2, further comprising repeating the identifying and the modifying on the array.

4. The method of claim 2, wherein the modifying further includes ensuring each individual TSV within a TSV set is on a predetermined grid for the IC layout regardless of position.

5. The method of claim 2, wherein all of the TSVs in each of the TSV sets in the IC layout initially extend in a single direction.

6. The method of claim 1, wherein the plurality of TSVs in the IC layout initially extend in a single direction.

7. The method of claim 1, wherein the portion includes a plurality of TSVs having different orientations, each TSV having a long edge and a short edge, and the identifying includes:

determining a layout direction of each of the plurality of TSVs, and

for each TSV, defining a selected TSV evaluation rectangle with a side thereof centered through the short edge of a selected TSV and extending in a given direction to an edge of the IC layout with a rectangle width set to a constant dimension and identifying each TSV that is linearly aligned with the selected TSV using the selected TSV evaluation rectangle; and

the modifying includes rotating each TSV that is linearly aligned with the selected TSV within the selected TSV evaluation rectangle to be non-aligned to the given direction.

8. The method of claim 5, further comprising determining the constant dimension based on a grid size of the IC layout.

9. A system comprising:

an identifier for identifying linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs; and

a modifier for modifying at least the portion of the IC layout to reduce a number of the linearly aligned TSVs.

10. The system of claim 9, wherein the portion includes an array of substantially uniform periodicity of through silicon via (TSV) sets, each of the TSV sets being arranged in a given direction, and the identifier:

defines a TSV set evaluation rectangle about each TSV set, each TSV set evaluation rectangle having a pair of X edges and a pair of Y edges,

calculates a Y spacing between adjacent TSV evaluation rectangles and an X spacing between adjacent TSV evaluation rectangles, and

expands each TSV evaluation rectangle edge, excepting at a chip edge, in at least one Y direction by half the Y spacing between adjacent TSV evaluation rectangles and in at least one X direction by half the X spacing between adjacent TSV evaluation rectangles; and

the modifier;

in response to a Y edge of a selected, expanded TSV evaluation rectangle contacting a Y edge of an adjacent, expanded TSV evaluation rectangle or an X edge of the selected, expanded TSV evaluation rectangle contacting an X edge of an adjacent, expanded TSV evaluation rectangle, rotates the TSV set within the selected TSV evaluation rectangle to be non-aligned to the given direction.

11. The system of claim 10, wherein the identifier and the modifier repeat the identifying and the modifying on the array.

12. The system of claim 10, wherein the modifier further ensures each individual TSV within a TSV set is on a predetermined grid for the IC layout regardless of position.

13. The system of claim 10, wherein all of the TSVs in the TSV sets in the IC layout initially extend in a single direction.

14. The system of claim 9, wherein the plurality of TSVs in the IC layout initially extend in a single direction.

15. The system of claim 9, wherein the portion includes a plurality of TSVs having different orientations, each TSV having a long edge and a short edge, and the identifier:

determines a layout direction of each of the plurality of TSVs, and

for each TSV, defines a selected TSV evaluation rectangle with a side thereof centered through the short edge of a selected TSV and extending in a given direction to an edge of the IC layout with a rectangle width set to a constant dimension and identifies each TSV that is linearly aligned with the selected TSV using the selected TSV evaluation rectangle; and

the modifier rotates each TSV that is linearly aligned with the selected TSV within the selected TSV evaluation rectangle to be non-aligned to the given direction.

16. The system of claim 15, wherein the constant dimension is based on a grid size of the IC layout.

17. A program product stored on a computer-readable medium, which when executed, arranges through silicon vias, the program product comprising:

program code for identifying linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs; and

program code for modifying at least the portion of the IC layout to reduce a number of the linearly aligned TSVs.

18. The program product of claim 17, wherein the portion includes an array of substantially uniform periodicity of through silicon via (TSV) sets, each of the TSV sets being arranged in a given direction, and the identifying program code includes program code for:

defining a TSV set evaluation rectangle about each TSV set, each TSV set evaluation rectangle having a pair of X edges and a pair of Y edges,

calculating a Y spacing between adjacent TSV evaluation rectangles and an X spacing between adjacent TSV evaluation rectangles, and

expanding each TSV evaluation rectangle edge, excepting at a chip edge, in at least one Y direction by half the Y spacing between adjacent TSV evaluation rectangles and in at least one X direction by half the X spacing between adjacent TSV evaluation rectangles; and

the modifying program code includes program code for;

in response to a Y edge of a selected, expanded TSV evaluation rectangle contacting a Y edge of an adjacent, expanded TSV evaluation rectangle or an X edge of the selected, expanded TSV evaluation rectangle contacting an X edge of an adjacent, expanded TSV evaluation rectangle, rotating the TSV set within the selected TSV evaluation rectangle to be non-aligned to the given direction.

19. The program product of claim 18, wherein the modifying program code further ensures each individual TSV within a TSV set is on a predetermined grid for the IC layout regardless of position.

20. The program product of claim 17, wherein the portion includes a plurality of TSVs having different orientations, each TSV having a long edge and a short edge, and the identifying program code includes program code for:

determining a layout direction of each of the plurality of TSVs, and

for each TSV, defining a selected TSV evaluation rectangle with a side thereof centered through the short edge of a selected TSV and extending in a given direction to an edge of the IC layout with a rectangle width set to a constant dimension and identifying each TSV that is linearly aligned with the selected TSV using the selected TSV evaluation rectangle; and

the modifying program code rotates each TSV that is linearly aligned with the selected TSV within the selected TSV evaluation rectangle to be non-aligned to the given direction.

21. An integrated circuit comprising:

a plurality of sets of through silicon vias (TSVs), each set including a plurality of TSVs aligned in a selected one of an x-direction and a y-direction, wherein a direction of a layout of the plurality of sets alternate in the x-direction and the y-direction.