ARRANGING THROUGH SILICON VIAS IN IC LAYOUT
First Claim
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1. A method comprising:
- identifying linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs; and
modifying at least the portion of the IC layout to reduce a number of the linearly aligned TSVs.
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Abstract
A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.
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Citations
21 Claims
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1. A method comprising:
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identifying linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs; and modifying at least the portion of the IC layout to reduce a number of the linearly aligned TSVs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system comprising:
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an identifier for identifying linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs; and a modifier for modifying at least the portion of the IC layout to reduce a number of the linearly aligned TSVs. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A program product stored on a computer-readable medium, which when executed, arranges through silicon vias, the program product comprising:
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program code for identifying linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs; and program code for modifying at least the portion of the IC layout to reduce a number of the linearly aligned TSVs. - View Dependent Claims (18, 19, 20)
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21. An integrated circuit comprising:
a plurality of sets of through silicon vias (TSVs), each set including a plurality of TSVs aligned in a selected one of an x-direction and a y-direction, wherein a direction of a layout of the plurality of sets alternate in the x-direction and the y-direction.
Specification