ZENER DIODE PROTECTION NETWORK IN SUBMOUNT FOR LEDS CONNECTED IN SERIES

• US 20110057569A1
• Filed: 09/09/2009
• Published: 03/10/2011
• Est. Priority Date: 09/09/2009
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Philips Lumileds Lighting Company LLC (Apollo Global Management, Inc.), Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: WEI, Yajun, COLLINS III, William D., STEIGERWALD, Daniel A.
• Granted Patent: US 8,400,064 B2
• Time in Patent Office: Days
• US Class Current: 315/122
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05B 45/48 having LEDs organised in strings and incorporating parallel shunting devices
• CPC Class Codes: H05B 45/54 in a series array of LEDs
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

A transient voltage suppressor circuit is disclosed for a plurality (N) of LEDs connected in series. Only one zener diode is created for connection to each node between LEDs, and a pair of zener diodes (the “end” zener diodes) are connected to the two pins (anode and cathode pads) of the series string. Therefore, only N+1 zener diodes are used. The end zener diodes (Q1 and Qn+1) effectively create back-to-back zener diodes across the two pins since the zener diodes share a common p+ substrate. The n+ regions of the end zener diodes Q1 and Qn+1 have the highest breakdown voltage requirement and must be placed relatively far apart. Adjacent n+ regions of the intermediate zener diodes have a much lower breakdown voltage requirement so may be located close together. Since there are fewer zener diodes and their spacings may be small, the zener diodes may be placed within a very small footprint or can be larger for better suppressor performance.

Claims

1. A light emitting device comprising:

N flip-chip light emitting diodes (LEDs) connected in series, the LEDs having electrodes and semiconductor light emitting surfaces, where N is two or more, wherein there is a node at each connection between LEDs, and wherein the LEDs comprise a first end LED having an anode connected to a first power terminal and a second end LED having a cathode connected to a second power terminal; and

a transient voltage suppression circuit connected to the N LEDs comprising a first end zener diode connected to the anode of the first end LED, a second end zener diode connected to the cathode of the second end LED, and only one intermediate zener diode per node connected to its associated node at each connection between LEDs.

2. The device of claim 1 further comprising:

a silicon submount on which the N LEDs are mounted, the silicon submount having formed in its surface the first end zener diode connected to the anode of the first end LED, the second end zener diode connected to the cathode of the second end LED, and the intermediate zener diode per node connected to its associated node, wherein the silicon submount is a p+ type and each zener diode is formed by a n+ region in a surface of the silicon submount; and

a patterned metal layer formed over a top surface of the silicon submount, the metal layer interconnecting all LEDs in series and connecting the zener diodes to the electrodes of the LEDs.

3. The device of claim 2 further comprising a metal contact electrically coupled to the p+ type silicon submount for connection to a bias voltage to bias the semiconductor light emitting surface of the LEDs during a photo-electrochemical (PEC) etch of the semiconductor light emitting surface of the LEDs.

4. The device of claim 3 wherein the semiconductor light emitting surfaces of the LEDs have been etched by PEC etching.

5. The device of claim 2 wherein N is greater than three and there are a plurality of intermediate zener diodes, wherein the n+ regions for adjacent intermediate zener diodes are spaced by a distance d1, and wherein the n+ regions for the first end zener diode and the second end zener diode are spaced by a distance d2, wherein d2 is larger than d1.

6. The device of claim 5 wherein the distances d1 and d2 are selected so that the intermediate zener diodes do not leak current at a normal operating voltage of the device.

7. The device of claim 2 wherein there are only N+1 zener diodes in the transient voltage suppression circuit for the N LEDs.

8. The device of claim 2 wherein the N LEDs are junction isolated LEDs formed in a single die, wherein the electrodes of the LEDs are all formed on a bottom surface of the LEDs facing the submount.

9. The device of claim 2 wherein the n+ regions of the first end zener diode and the second end zener diode are wider than the n+ region of each intermediate zener diode.

10. The device of claim 2 wherein each n+ region of an intermediate zener diode interconnects electrodes of two LEDs in series.

11. The device of claim 2 wherein the N LEDs comprises an array of LEDs.

12. The device of claim 2 wherein the first end zener diode and the second end zener diode pair have a breakdown voltage above a normal operating voltage of the string of N LEDs connected in series, and at least some of the intermediate zener diodes have a breakdown voltage below the normal operating voltage of the string of N LEDs connected in series.

13. The device of claim 2 wherein the n+ regions of the intermediate zener diodes are formed underneath the N LEDs, and a majority of the n+ region of the first end zener diode and the second end zener diode are not formed underneath the N LEDs.

14. The device of claim 2 wherein the N LEDs are formed in a single die, and all intermediate zener diodes are formed underneath the die with the distance between adjacent intermediate zener diodes being smaller than that required to withstand a first voltage across the adjacent intermediate zener diodes without breaking down, wherein the first voltage is equal to a maximum operating voltage connected across the N LEDs connected in series, wherein at least portions of the first end zener diode and second end zener diode extend beyond a border of the die.

15. A method comprising:

providing on a silicon submount N flip-chip light emitting diodes (LEDs) connected in series, the LEDs having electrodes and semiconductor light emitting surfaces, where N is three or more, wherein there is a node at each connection between LEDs, and wherein the LEDs comprise a first end LED having an anode connected to a first power terminal and a second end LED having a cathode connected to a second power terminal,

the silicon submount having formed in and on it a transient voltage suppression circuit connected to the N LEDs comprising a first end zener diode connected to the anode of the first end LED, a second end zener diode connected to the cathode of the second end LED, and only one intermediate zener diode per node connected to its associated node at each connection between LEDs, wherein the silicon submount is a p+ type and each zener diode is formed by a n+ region in a surface of the silicon submount,

a patterned metal layer being formed over a top surface of the silicon submount, the metal layer interconnecting all LEDs in series and connecting the zener diodes to the electrodes of the LEDs;

connecting a bias voltage to the p+ type material in the silicon submount to electrically bias the semiconductor light emitting surfaces of the N LEDs via the p+ material and the zener diodes;

immersing the semiconductor light emitting surfaces in an electrolyte solution; and

performing photo-electrochemical etching (PEC) of the semiconductor light emitting surfaces.