POWER MODULE

• US 20110057713A1
• Filed: 09/08/2010
• Published: 03/10/2011
• Est. Priority Date: 06/12/2008
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Yaskawa Denki
• Original Assignee: Kabushiki Kaisha Yaskawa Denki
• Inventors: ISOBE, Tasuku, KAWANAMI, Yasuhiko
• Granted Patent: US 8,279,605 B2
• Time in Patent Office: Days
• US Class Current: 327/427
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01065 Terbium [Tb]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

The present invention provides a power module in which a first semiconductor device disposed on a first substrate and a second semiconductor device disposed on a second substrate are disposed at symmetrical positions with a third substrate interposed therebetween.

Claims

1. A power module comprising:

a first semiconductor device provided with a first FET;

a first substrate on a surface of which the first semiconductor device is disposed;

a second semiconductor device provided with a second FET that is electrically connected in series to the first FET;

a second substrate on a surface of which the second semiconductor device is disposed; and

a third substrate disposed between the first semiconductor device on the first substrate and the second semiconductor device on the second substrate, the third substrate being electrically connected to the first FET and the second FET, wherein

the first semiconductor device and the second semiconductor device are disposed at symmetrical positions with third substrate interposed therebetween

a first metallic plate and a second metallic plate are respectively disposed on a surface of the third substrate and a back surface facing away of the surface, and the first metallic plate and the second metallic plate are respectively connected with the first semiconductor device and the second semiconductor device,

the third substrate has a function of a capacitor for accumulating a charge, and

a plurality of metallic layers and a plurality of insulation layers are formed between the first metallic plate and the second metallic plate.

2. The power module according to claim 1, further comprising:

a first inverter circuit provided with the first FET, the second FET, and a first connection node to which the first FET and the second FET are connected;

a second inverter circuit provided with a third FET formed within a third semiconductor device disposed on the first substrate, and a fourth FET formed within a fourth semiconductor device disposed on the second substrate and electrically connected in series to the third FET, and a second connection node to which the third FET and the fourth FET are connected; and

a third inverter circuit provided with a fifth FET formed within a fifth semiconductor device disposed on the first substrate, a sixth FET formed within a sixth semiconductor device disposed on the second substrate and electrically connected in series to the fifth FET, and a third connection node to which the fifth FET and the sixth FET are connected, wherein

the first to third connection nodes are connected to an output terminal.

3. The power module according to claim 2, wherein

the first to sixth FETs are respectively provided with parasitic diodes.

4. The power module according to claim 3, wherein

on the third substrate, elements for driving the first to sixth FETs are mounted.

5. The power module according to claim 4, further comprising:

a first heat sink formed on a back surface facing away of the surface of the first substrate; and

a second heat sink formed on a back surface facing away of the surface of the second substrate.

6. A control device for a motor that controls the motor using the power module according to claim 5.

7. The control device for a motor according to claim 6, wherein

the power module is disposed adjacent to a cooling tube through which a cooling fluid flows.

8. The control device for a motor according to claim 7, wherein

the cooling tube is provided with a first cooling unit and a second cooling unit, and

the power module is disposed between the first cooling unit and the second cooling unit.

9. A method of controlling the power module according to claim 1, comprising:

a first step in which the second FET is substantially in an off state when the first FET is turned on; and

a second step in which the first FET is substantially in an off state when the second FET is turned on.

10. The method of controlling a power module according claim 9, wherein

the first step and the second step are alternately repeated.

11. A power module comprising:

a first semiconductor device configured by SiC or GaN as a material;

a first substrate on a surface of which the first semiconductor device is disposed;

a second semiconductor device electrically connected in series to the first semiconductor device and configured by SiC or GaN as a material;

a second substrate on a surface of which the second semiconductor device is disposed; and

a third substrate disposed between the first semiconductor device on the first substrate and the second semiconductor device on the second substrate, and electrically connected to the first semiconductor device and the second semiconductor device, wherein

the first semiconductor device and the second semiconductor device are disposed at symmetrical positions with third substrate interposed therebetween,

a first metallic plate and a second metallic plate are respectively disposed on a surface of the third substrate and aback surface facing away of the surface, and the first metallic plate and the second metallic plate are respectively connected with the first semiconductor device and the second semiconductor device,

the third substrate has a function of a capacitor for accumulating a charge, and

a plurality of metallic layers and a plurality of insulation layers are formed between the first metallic plate and the second metallic plate.

12. The power module according to claim 11, wherein

the power module is disposed adjacent to a cooling tube through which a cooling fluid flows.

13. The power module according to claim 12, wherein

the cooling tube is provided with a first cooling unit and a second cooling unit, and

the power module is disposed between the first cooling unit and the second cooling unit.

14. A power module comprising:

a first semiconductor device provided with a first FET,

a first substrate electrically connected to the first semiconductor device;

a second semiconductor device provided with a second FET;

a second substrate on a surface of which the second semiconductor device is disposed; and

a third substrate on a surface of which and a back surface facing away of the surface a first metallic plate and a second metallic plate are respectively disposed, the first metallic plate and the second metallic plate being respectively connected with the first semiconductor device and the second semiconductor device, wherein

the third substrate has a function of a capacitor for accumulating a charge, and

a plurality of metallic layers and a plurality of insulation layers are formed between the first metallic plate and the second metallic plate.