Holographic Display

• US 20110057932A1
• Filed: 08/29/2008
• Published: 03/10/2011
• Est. Priority Date: 08/31/2007
• Status: Abandoned Application

• Current Assignee: SeeReal Technologies S.A.
• Original Assignee: SeeReal Technologies S.A.
• Inventors: Schwerdtner, Alexander, Missbach, Robert
• Application Number:
  US12/674,973
• Publication Number:
  US 20110057932A1
• Time in Patent Office: Days
• US Class Current: 345/426
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A holographic display is provided in which at least one spatial light modulator has a hierarchical structure of the column drivers, the function of the column drivers being distributed to n units which are connected in n cascading stages, where n is two or more, with each successive stage having slower speed circuitry than the previous stage.

Claims

1. A holographic display in which at least one spatial light modulator has a hierarchical structure of the column drivers, the function of the column drivers being distributed to n units which are connected in n cascading stages, where n is two or more, with each successive stage having slower speed circuitry than the previous stage.

2. The holographic display of claim 1, wherein each successive stage having slower speed circuitry is made from a different semiconductor material to the semiconductor material in the previous stage.

3. The holographic display of claim 1, wherein n is three.

4. The holographic display of claim 1, wherein the holographic display has two SLMs, which permit independent modulation of phase and amplitude.

6. The holographic display of claim 1, wherein the holographic display has one SLM.

7. The holographic display of claim 1, wherein at least one spatial light modulator with a hierarchical structure of the column drivers is a liquid crystal SLM or wherein at least one spatial light modulator with a hierarchical structure of the column drivers is a micro mirror device or wherein at least one spatial light modulator with a hierarchical structure of the column drivers is an electrically addressable SLM.

10. The holographic display of claim 7, wherein at least one spatial light modulator with a hierarchical structure of the column drivers is a MOSLM or wherein at least one spatial light modulator with a hierarchical structure of the column drivers is an OASLM.

12. The holographic display of claim 1, wherein the holographic display displays a computer generated hologram and wherein the holographic display produces at least one virtual observer window.

14. The holographic display of claim 2, wherein the higher or the highest speed circuitry is made using InP technology or is made by using InSb technology, or is made by using GaAs technology, or is made by using SiGe technology.

18. The holographic display of claim 2, wherein the higher speed circuitry is made using c-Si technology or wherein the lower speed circuitry is made using c-Si technology.

20. The holographic display of claim 2, wherein the lower or lowest speed circuitry is made using p-Si technology.

21. The holographic display of claim 1, wherein the at least one SLM has a minimum pixel resolution of 2,400×

1,600 pixels.

22. The holographic display of claim 1, wherein the at least one SLM has a minimum frame rate of 100 Hz.

23. The holographic display of claim 1, wherein the at least one SLM has greater than 50 million pixels and a frame rate of less than 100 Hz.

24. The holographic display of claim 1, which is spatially multiplexed, with a frame rate less than 100 Hz, and with a column frequency of 40 kHz or greater.

25. The holographic display of claim 1, wherein a control frequency on the row wires and column wires of the at least one SLM is at least 1 MHz.

26. The holographic display of claim 1, wherein the holographic display has a display panel glass substrate.

27. The holographic display of claim 26, wherein the holographic display panel glass substrate is connected to a panel electronic PCB or wherein the holographic display panel glass substrate is connected to a panel electronic PCB with an intermediate flexible PCB stage.

29. The holographic display of claim 14, wherein the higher or the highest speed circuitry is applied directly on to a glass display panel substrate, using Chip on Glass (COG) technology.

30. A method of demultiplexing high speed data provided to a holographic display, the holographic display being one in accordance with claim 1.

5. (canceled)

8-9. -9. (canceled)

11. (canceled)

13. (canceled)

15-17. -17. (canceled)

19. (canceled)

28. (canceled)