SEMICONDUCTOR INTEGRATED CIRCUIT, DISPLAY DEVICE, AND DISPLAY CONTROL METHOD

• US 20110057949A1
• Filed: 09/02/2010
• Published: 03/10/2011
• Est. Priority Date: 09/08/2009
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: SAITOU, Tsukasa
• Application Number:
  US12/874,915
• Publication Number:
  US 20110057949A1
• Time in Patent Office: Days
• US Class Current: 345/596
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0414 Vertical resolution change
• CPC Class Codes: G09G 2340/0421 Horizontal resolution change
• CPC Class Codes: G09G 2370/04 Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
• CPC Class Codes: G09G 3/2044 using dithering
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 5/005 Adapting incoming signals to the display format of the display terminal
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A semiconductor integrated circuit includes a plurality of data hold circuits that are associated with a plurality of pixel columns arranged in a pixel arranged area where a plurality of pixels are arranged in matrix, each of the plurality of data hold circuits being configured to hold data which is to be supplied to the pixel column; and a plurality of selectors, each selector being configured to selectively supply, based on whether a shift process for dithering is to be performed or not, one of outputs of a pair of data hold circuits coupled to said selector to the pixel column included in a pair of pixel columns that is associated with said pair of data hold circuits, said pair of pixel columns comprising pixel columns positioned side by side in the pixel arranged area.

Claims

1. A semiconductor integrated circuit comprising:

a plurality of data hold circuits that are associated with a plurality of pixel columns arranged in a pixel arranged area where a plurality of pixels are arranged in matrix, each of the plurality of data hold circuits being configured to hold data which is to be supplied to the pixel column; and

a plurality of selectors, each selector being configured to selectively supply, based on whether a shift process for dithering is to be performed or not, one of outputs of a pair of data hold circuits coupled to said selector to the pixel column included in a pair of pixel columns that is associated with said pair of data hold circuits, said pair of pixel columns comprising pixel columns positioned side by side in the pixel arranged area.

2. The semiconductor integrated circuit according to claim 1, wherein when performing the shift process, each selector supplies the output of the data hold circuit that is not associated with said pixel column included in the pair of pixel columns to which the data is supplied from the selector.

3. The semiconductor integrated circuit according to claim 1, wherein

the pixel arranged area includes N pixel columns, N indicating a natural number of 2 or more, and

N−

1 selectors are associated with N−

1 pairs of pixel columns included in the N pixel columns.

4. The semiconductor integrated circuit according to claim 1, further comprising:

a control signal generator that generates a control signal for setting selection states of the selectors, wherein

the control signal generator generates the control signal based on information indicating which pixel line the data held by the plurality of data hold circuits are supplied to.

5. The semiconductor integrated circuit according to claim 4, wherein the control signal generator generates the control signal based on number of frame of an image to be displayed in addition to said information.

6. The semiconductor integrated circuit according to claim 4, wherein

the control signal generator operates based on a determination signal for determining whether to generate the control signal or not, and

a signal value of the determination signal is determined by whether to perform dithering or not against a sub-area that is formed by dividing the pixel arranged area.

7. The semiconductor integrated circuit according to claim 1, wherein, when dithering is being performed, the same data are held in the same group of data hold circuits which are defined by grouping the plurality of data hold circuits.

8. The semiconductor integrated circuit according to claim 3, further comprising N source amplifiers that are associated with the N pixel columns.

9. The semiconductor integrated circuit according to claim 8, wherein the N source amplifiers include:

a first source amplifier coupled between the data hold circuit and the pixel column; and

a plurality of second source amplifiers, each second source amplifier being coupled between the selector and the pixel column.

10. The semiconductor integrated circuit according to claim 1, wherein the plurality of data hold circuits include first to third data hold circuits and the plurality of selectors include first and second selectors, and wherein

outputs of the first and second data hold circuits are respectively supplied to first and second input terminals of the first selector, and outputs of the second and third data hold circuits are respectively supplied to first and second input terminals of the second selector.

11. The semiconductor integrated circuit according to claim 10, wherein selection states of the first and second selectors are determined by a common control signal supplied from a control signal generator.

12. The semiconductor integrated circuit according to claim 11, further comprising first to third source amplifiers,

wherein the first source amplifier receives data output from the first data hold circuit, the second source amplifier receives data output from the first selector, and the third source amplifier receives data output from the second selector.

13. A display device comprising:

the semiconductor integrated circuit of claim 1; and

an image display unit that displays an image on the pixel arranged area.

14. A display control method comprising:

holding data by a plurality of data hold circuits that are associated with a plurality of pixel columns included in a pixel arranged area where a plurality of pixels are arranged in matrix; and

selectively supplying one of outputs of a pair of data hold circuits to the pixel column included in a pair of pixel columns, which is associated with said pair of data hold circuits and comprises pixel columns positioned side by side in the pixel arranged area, based on whether a shift process for dithering is to be performed or not.

15. The display control method according to claim 14, wherein when performing the shift process, the output of the data hold circuit, which is not associated with said pixel column of the pair of pixel columns to which the data is supplied from the selector, is supplied to said pixel column of the pair of pixel columns.

16. The display control method according to claim 15, wherein a period of performing the shift process is determined based on information indicating which pixel line the data held in the plurality of data hold circuits are supplied to.