MRAM DIODE ARRAY AND ACCESS METHOD

• US 20110058409A1
• Filed: 11/18/2010
• Published: 03/10/2011
• Est. Priority Date: 10/20/2008
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Lu, Yong, Liu, Hongyue, Xue, Song S., Li, Hai, Chen, Yiran
• Granted Patent: US 8,289,746 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

Claims

1. A memory unit comprising:

a magnetic tunnel junction data cell electrically coupled to a bit line and a source line, the magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell;

a first diode electrically between the magnetic tunnel junction data cell and the source line; and

a second diode electrically between the magnetic tunnel junction data cell and the source line, the first diode and second diode in parallel electrical connection, and having opposing forward bias directions

wherein the memory unit is configured to be precharged to a specified precharge voltage level, the precharge voltage being less than a threshold voltage of the first diode and second diode.

2. A memory unit according to claim 1, wherein the specified precharge voltage level is in a range from 40 to 60% of a write voltage.

3. A memory unit according to claim 1, wherein the memory unit does not include a transistor electrically between the bit line and the source line.

4. A memory unit according to claim 1, wherein the first diode provides current to the magnetic tunnel junction data cell to switch the magnetic tunnel junction data cell from a high resistance state to a low resistance state and the second diode provides current to the magnetic tunnel junction data cell to switch the magnetic tunnel junction data cell from a low resistance state to a high resistance state.

5. A memory unit according to claim 1, wherein the magnetic tunnel junction data cell is a spin-transfer torque data cell.

6. A memory unit according to claim 1, wherein the first diode is a p-n junction and the second diode is a p-n junction.

7. A memory array, comprising:

a plurality of bit lines;

a plurality of source lines intersecting with the plurality of bit lines and forming a cross-point array;

a memory unit adjacent to at least selected cross-points of the cross-point array, the memory unit comprising;

a magnetic tunnel junction data cell electrically coupled to a bit line and a source line, the magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell;

a first diode electrically between the magnetic tunnel junction data cell and the source line; and

a second diode electrically between the magnetic tunnel junction data cell and the source line, the first diode and second diode in parallel electrical connection, and having opposing forward bias directions;

wherein the memory array is configured to be precharged to a specified precharge voltage level, the precharge voltage being less than a threshold voltage of the first diode and second diode.

8. A memory array according to claim 7, wherein the specified precharge voltage level is in a range from 40 to 60% of a write voltage.

9. A memory unit according to claim 7, wherein the memory unit does not include a transistor electrically between the bit line and the source line.

10. A memory unit according to claim 7, wherein the first diode provides current to the magnetic tunnel junction data cell to switch the magnetic tunnel junction data cell from a high resistance state to a low resistance state and the second diode provides current to the magnetic tunnel junction data cell to switch the magnetic tunnel junction data cell from a low resistance state to a high resistance state.

11. A memory unit according to claim 7, wherein the magnetic tunnel junction data cell is a spin-transfer torque data cell.

12. A memory unit according to claim 7, wherein the first diode is a p-n junction and the second diode is a p-n junction.

13. A method comprising:

precharging a plurality of magnetic tunnel junction data cells to a specified precharge voltage level in a range from 40 to 60% of a write voltage, each magnetic tunnel junction data cell includes a first diode and a second diode in parallel electrical connection and having opposing forward bias directions, the precharge voltage being less than a threshold voltage of the first diode and second diode;

switching a magnetic tunnel junction data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction, the write current provided by a first diode being electrically coupled to the magnetic tunnel junction data cell and a source line; and

switching the magnetic tunnel junction data cell from a low resistance state to a high resistance state by passing a write current through the magnetic tunnel junction data cell in a second direction opposing the first direction, the write current provided by a second diode being electrically coupled to the magnetic tunnel junction data cell and a source line and in parallel electrical connection with the first diode.

14. A method according to claim 13, wherein the write current provided by a first diode is substantially the same magnitude as the write current provided by a second diode.

15. A method according to claim 13, further comprising precharging a plurality of bit lines and a plurality of source lines to a precharge voltage being less than a threshold voltage of the first diode and second diode, the plurality source lines intersecting with the plurality of bit lines and forming a cross-point array, and the magnetic tunnel junction data cell adjacent to at least selected cross-points of the cross-point array, the first diode and second diode are electrically between the magnetic tunnel junction data cell and the source line.

16. A method according to claim 15, further comprising writing a first data state to one or more magnetic tunnel junction data cells along a selected bit line by applying a write voltage to the selected bit line and grounding one or more selected source lines.

17. A method according to claim 15, further comprising reading a data state from a selected magnetic tunnel junction data cell by applying a read voltage to a selected bit line and grounding a selected source line.

18. A method according to claim 15, further comprising reading a data state from a selected magnetic tunnel junction data cell by applying a read voltage to a selected source line and grounding a selected bit line.

19. A method according to claim 15, wherein the precharge voltage is about 50% of the writing voltage.

20. A method according to claim 16, further comprising writing a second data state to one or more magnetic tunnel junction data cells along the selected bit line by applying a write voltage to the selected bit line and grounding one more selected source lines.