Circuits, Architectures, Apparatuses, Systems, Algorithms, and Methods for Memory with Multiple Power Supplies and/or Multiple Low Power Modes
First Claim
1. A dual power supply memory, comprising:
- peripheral circuitry operating at a first voltage;
a memory array operating at a second voltage; and
translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage from a power rail providing the second voltage.
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Accused Products
Abstract
Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.
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Citations
26 Claims
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1. A dual power supply memory, comprising:
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peripheral circuitry operating at a first voltage; a memory array operating at a second voltage; and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage from a power rail providing the second voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A memory, comprising:
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peripheral circuitry receiving a first voltage from a peripheral power rail; a memory array receiving the first voltage or a second voltage from a memory array power rail; a diode or a bias source coupled serially between a ground plane in the memory array and an external ground potential; and a leakage reduction switch coupled serially between the ground plane in the memory array and the external ground potential, the leakage reduction switch configured to selectively bypass the diode or the bias source. - View Dependent Claims (17, 18, 19, 20)
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21. A method for reducing power consumption in a memory, the method comprising:
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operating peripheral circuitry at a first voltage, wherein the peripheral circuitry is coupled to a first power rail; operating a memory array at the first voltage or a second voltage, wherein the second voltage is different from the first voltage, and the memory array is coupled to a second power rail; coupling the first and second power rails when the memory array operates at the first voltage, otherwise not coupling the first and second power rails; and reducing leakage in the memory array during a power down or leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification