LED HAVING VERTICAL STRUCTURE AND METHOD FOR FABRICATING THE SAME

• US 20110059564A1
• Filed: 09/08/2010
• Published: 03/10/2011
• Est. Priority Date: 12/15/2005
• Status: Active Grant

• Current Assignee: Suzhou Lekin Semiconductor Company Limited
• Original Assignee: LG Electronics, Inc. (LG Corporation), LG Innotek Company Limited (LG Corporation)
• Inventors: NA, Jong Ho, CHOI, Jae Wan, JANG, Jun Ho, CHO, Hyun Kyong, KIM, Jong Wook
• Granted Patent: US 8,202,753 B2
• Time in Patent Office: Days
• US Class Current: 438/46
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate

Abstract

A light emitting diode (LED) having a vertical structure and a method for fabricating the same. The light emitting diode (LED) having a vertical structure includes a support layer; a first electrode formed on the support layer; a plurality of semiconductor layers formed on the first electrode; a conductive semiconductor layer formed on the plurality of semiconductor layers, and provided with an outer surface having a tilt angle of a designated degree; and a second electrode formed on the conductive semiconductor layer.

Claims

1. A method for fabricating a light emitting diode, comprising:

forming a mask layer on a substrate;

forming a conductive semiconductor layer on the mask layer;

forming a plurality of semiconductor layers on the conductive semiconductor layer, the conductive semiconductor layer serving as a template for the semiconductor layers, wherein the conductive semiconductor layer has a side surface having a tilt angle;

forming a first electrode on the plurality of semiconductor layers;

forming a support layer on the first electrode;

separating the substrate; and

forming a second electrode on a surface of the conductive semiconductor layer.

2. The method according to claim 1, wherein the mask layer is formed on a buffer layer.

3. The method according to claim 2, wherein the buffer layer comprises a gallium nitride-based semiconductor (Al_xIn_yGa_1-x-yN:

0≦

(x,y)≦

1) layer.

4. The method according to claim 1, wherein forming the mask layer comprises:

forming a dielectric layer on the substrate; and

patterning the dielectric layer into a circular or polygonal shape.

5. The method according to claim 4, wherein a horizontal sectional shape of the conductive semiconductor layer is substantially the same as the circular or polygonal shape of the dielectric layer.

6. The method according to claim 4, wherein a horizontal sectional shape of the conductive semiconductor layer has more sides than the polygonal shape of the dielectric layer.

7. The method according to claim 1, wherein the dielectric layer comprises silicon oxide or silicon nitride.

8. The method according to claim 1, wherein the conductive semiconductor layer comprises a conductive GaN layer having a thickness of 1˜

300 μ

m.

9. The method according to claim 1, wherein the conductive semiconductor layer is formed by a hydride vapor phase epitaxy (HVPE) method.

10. The method according to claim 1, wherein forming the plurality of semiconductor layers comprises:

forming an n-type semiconductor layer on the conductive semiconductor layer;

forming a light emitting layer on the n-type semiconductor layer; and

forming a p-type semiconductor layer on the light emitting layer.

11. The method according to claim 1, wherein the substrate comprises a GaN substrate formed by a hydride vapor phase epitaxy (HVPE) method.

12. The method according to claim 1, wherein the plurality of semiconductor layers are formed by a metal organic chemical vapor deposition (MOCVD) method.

13. The method according to claim 1, wherein separating the substrate is performed by a laser lift-off process or a wet etching process.

23. The method according to claim 1, wherein the first electrode comprises:

an electrical contact; and

a reflective electrode on the electrical contact.

24. The method according to claim 1, wherein the first electrode comprises a reflective ohmic electrode.

25. The method according to claim 1, wherein the tilt angle of the conductive semiconductor layer is an angle of the side surface with respect to the surface of the conductive semiconductor layer, which is in the range of 35˜

65°

.

26. The method according to claim 1, wherein at least one of the support layer, the first electrode, the semiconductor layers, the conductive semiconductor layer, and the second electrode has a horizontal sectional shape of a polygon, which is more than a rectangle.

27. The method according to claim 1, wherein the support layer comprises at least one of a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, a germanium (Ge) substrate, a metal substrate including nickel (Ni) or copper (Cu), and a substrate including metal.

28. The method according to claim 1, wherein the conductive semiconductor layer is configured to improve the light extraction efficiency.

29. The method according to claim 1, wherein the conductive semiconductor layer is thicker than the semiconductor layers.

30. The method according to claim 1, wherein the semiconductor layers is in direct contact with the conductive semiconductor layer.

31. The method according to claim 1, further comprising forming a seed metal on the first electrode.

32. The method according to claim 1, wherein a side surface of the semiconductor layers has a tilt angle different from the tilt angle of the conductive semiconductor layer.

33. The method according to claim 1, wherein the tilt angle of the conductive semiconductor layer is an angle of the side surface with respect to the surface of the conductive semiconductor layer, which is in the range of 53˜

56°

.

34. The method according to claim 1, wherein the tilt angle of the conductive semiconductor layer is configured such that the surface of the conductive semiconductor layer is larger than a surface of the conductive semiconductor layer contacting the semiconductor layers.

35. The method according to claim 1, wherein the side surface of the conductive semiconductor layer is configured to reduce a possibility of internal total reflection of the light emitted from the semiconductor layers, thereby improving the light extraction efficiency of the diode.

36. The method according to claim 1, wherein the conductive semiconductor layer is configured to emit the light from the semiconductor layers through the surface of the conductive semiconductor layer.

14-22. -22. (canceled)