SEMICONDUCTOR DEVICE

• US 20110059586A1
• Filed: 11/11/2010
• Published: 03/10/2011
• Est. Priority Date: 12/10/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamaguchi, Yoshihiro, Kawaguchi, Yusuke, AKIYAMA, Miwako
• Granted Patent: US 9,105,716 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.

Claims

1. A method for producing a semiconductor device, comprising:

forming a structure in which a trench gate structure is provided in a front surface side of semiconductor layers in which on a main surface of a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type that has a lower impurity concentration than that of the first semiconductor layer, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of the first conductivity type are sequentially provided;

forming a contact groove passing through the fourth semiconductor layer in the contiguous trench gate structures and reaching the third semiconductor layer; and

forming a fifth semiconductor layer by introducing an impurity of the second conductive type into the second semiconductor layer by a plurality of times sequentially from a first introduction position in the second semiconductor layer not reaching the main surface of the first semiconductor layer to a shallower position therein in the third semiconductor layer side so that the fourth semiconductor layer in which the contact grooves are selectively formed serves as a mask,

the fifth semiconductor layer being thinner from an uppermost portion to a lowermost portion, and

a dose amount in impurity introduction into the first introduction position being higher than a dose amount of impurity introduction into the shallower position than the first introduction position.

2. The method for producing a semiconductor device according to claim 1, wherein the fifth semiconductor layer is thinner in a stepwise manner.

3. The method for producing a semiconductor device according to claim 1, wherein width of the contact groove is narrower as depth thereof to the third semiconductor layer is larger.

4. The method for producing a semiconductor device according to claim 3, wherein the width of the contact groove is narrowed continuously.

5. The method for producing a semiconductor device according to claim 3, wherein the width of the contact groove is narrowed in a stepwise manner.

6. The method for producing a semiconductor device according to claim 1, wherein width of the contact groove is about constant in the depth direction.

7. The method for producing a semiconductor device according to claim 6, wherein the width of the contact groove is made to be sequentially wider by the times of impurity introduction from the impurity introduction into the first introduction position to the impurity introduction into the shallower position than the first introduction position.

8. The method for producing a semiconductor device according to claim 6, wherein the impurity introduction is performed from the direction inclined to both directions of parallel direction and perpendicular direction to the main surface of the first semiconductor layer.

9. The method for producing a semiconductor device according to claim 1, wherein the impurity introduction is performed by an ion implantation method, and the producing method further includes diffusing the impurity by heat treatment after the implantation.

10. The method for producing a semiconductor device according to claim 9, wherein the implanted impurity more largely diffuses to the horizontal direction as the position thereof is shallower.