Systems and Methods for Flash Memory Utilization

• US 20110060865A1
• Filed: 04/30/2010
• Published: 03/10/2011
• Est. Priority Date: 09/08/2009
• Status: Abandoned Application

• Current Assignee: LSI Corporation (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Ober, Robert E., Dreifus, David L., Warren, Robert W.
• Application Number:
  US12/772,005
• Publication Number:
  US 20110060865A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a non-volatile memory, a flash memory, and a read/write controller circuit. The read/write controller circuit is coupled to both the flash memory and the non-volatile memory, and is operable to receive a data set directed to the flash memory and to direct the data set to the random access memory.

Claims

1. A memory system, the memory system comprising:

a non-volatile memory;

a flash memory; and

a read/write controller circuit, wherein the read/write controller circuit is coupled to both the flash memory and the non-volatile memory, and wherein the read/write controller circuit is operable to receive a data set directed to the flash memory and to direct the data set to the non-volatile memory.

2. The memory system of claim 1, wherein directing the data set to the non-volatile memory extends a lifecycle of the flash memory.

3. The memory system of claim 1, wherein the read/write controller circuit is further operable to direct a read request for the data set to the non-volatile memory.

4. The memory system of claim 3, wherein the read/write controller circuit is further operable to transfer a data block from the non-volatile memory to the flash memory to make room for the data set in the non-volatile memory.

5. The memory system of claim 4, wherein the data block is selected by the read/write controller circuit using a replacement algorithm.

6. The memory system of claim 5, wherein the replacement algorithm is a least recently used algorithm.

7. The memory system of claim 4, wherein the memory system further comprises:

a wear leveling circuit, wherein the wear leveling circuit is operable to select a location in the flash memory to receive the data block.

8. The memory system of claim 7, wherein the wear leveling circuit implements a wear leveling algorithm that seeks to evenly spread writes across cells of the flash memory.

9. The memory system of claim 1, wherein the read/write controller circuit and the non-volatile memory are implemented on the same chip.

10. The memory system of claim 1, wherein the read/write controller circuit, the non-volatile memory, and the flash memory are combined into a replaceable memory subsystem.

11. The memory system of claim 10, wherein the replaceable memory subsystem is a solid state disk drive.

12. The memory system of claim 1, wherein the flash memory is implemented on a replaceable flash memory unit apart from the read/write controller circuit and the non-volatile memory.

13. The memory system of claim 1, wherein directing the data set to the non-volatile memory reduces a number of writes to the flash memory.

14. A method for data storage, the method comprising:

providing a memory system having a non-volatile memory and a flash memory;

receiving a first data set;

writing the first data set to the non-volatile memory;

receiving a second data set;

transferring the first data set to the flash memory; and

writing the second data set to the non-volatile memory.

15. The method of claim 14, wherein the method further comprises:

receiving a read request for the second data set; and

accessing the second data set from the non-volatile memory.

16. The method of claim 14, wherein the method further comprises:

receiving a read request for the first data set; and

accessing the first data set from the flash memory.

17. The method of claim 14, wherein the method further comprises:

applying a replacement algorithm to data in the non-volatile memory, wherein the first data set is selected to be transferred to the flash memory based at least in part on application of the replacement algorithm.

18. The method of claim 14, wherein the method further comprises:

applying a wear leveling algorithm to determine a location in the flash memory to which the first data set is written.

19. The method of claim 18, wherein the wear leveling algorithm operates evenly spread writes across cells of the flash memory.

20. A computer system, the computer system comprising:

a processor;

a memory system accessible by the processor, wherein the memory system includes;

a non-volatile memory;

a flash memory; and

a read/write controller circuit, wherein the read/write controller circuit is coupled to both the flash memory and the random access memory, and wherein the read/write controller circuit is operable to receive a data set directed to the flash memory and to direct the data set to the random access memory such that a lifecycle of the flash memory is extended.